################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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ZYNQ 7010驱动触摸屏(FPGA驱动).zip
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ZYNQ 7010驱动触摸屏(FPGA驱动).zip (222个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
top_lcd_touch.bit 1.99MB
top_lcd_touch_routed.dcp 1.01MB
top_lcd_touch_placed.dcp 862KB
top_lcd_touch_opt.dcp 562KB
top_lcd_touch.dcp 347KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
clk_wiz_0.dcp 9KB
compile.do 687B
compile.do 663B
compile.do 622B
compile.do 612B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 195B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 474B
run.f 458B
usage_statistics_webtalk.html 31KB
usage_statistics_ext_labtool.html 3KB
.xsim_webtallk.info 59B
xsim.ini 22KB
vivado.jou 829B
vivado.jou 820B
vivado.jou 815B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 73KB
runme.log 39KB
runme.log 24KB
labtool_webtalk.log 402B
top_lcd_touch.lpr 343B
elab.opt 188B
vivado.pb 122KB
vivado.pb 38KB
place_design.pb 24KB
opt_design.pb 17KB
route_design.pb 15KB
write_bitstream.pb 5KB
init_design.pb 4KB
top_lcd_touch_power_summary_routed.pb 722B
clk_wiz_0_utilization_synth.pb 224B
top_lcd_touch_utilization_placed.pb 224B
top_lcd_touch_utilization_synth.pb 224B
vivado.pb 149B
top_lcd_touch_timing_summary_routed.pb 106B
top_lcd_touch_methodology_drc_routed.pb 53B
top_lcd_touch_route_status.pb 44B
top_lcd_touch_drc_routed.pb 37B
top_lcd_touch_drc_opted.pb 37B
top_lcd_touch_bus_skew_routed.pb 30B
vlog.prj 251B
top_lcd_touch_timing_summary_routed.rpt 136KB
top_lcd_touch_io_placed.rpt 118KB
top_lcd_touch_methodology_drc_routed.rpt 42KB
top_lcd_touch_clock_utilization_routed.rpt 17KB
top_lcd_touch_utilization_placed.rpt 9KB
top_lcd_touch_power_routed.rpt 9KB
top_lcd_touch_drc_routed.rpt 7KB
top_lcd_touch_control_sets_placed.rpt 7KB
top_lcd_touch_utilization_synth.rpt 7KB
top_lcd_touch_drc_opted.rpt 7KB
clk_wiz_0_utilization_synth.rpt 6KB
top_lcd_touch_bus_skew_routed.rpt 930B
top_lcd_touch_route_status.rpt 588B
top_lcd_touch_power_routed.rpx 584KB
top_lcd_touch_timing_summary_routed.rpx 161KB
top_lcd_touch_methodology_drc_routed.rpx 76KB
top_lcd_touch_drc_routed.rpx 10KB
top_lcd_touch_drc_opted.rpx 9KB
top_lcd_touch_bus_skew_routed.rpx 1KB
.route_design.begin.rst 189B
.opt_design.begin.rst 189B
.write_bitstream.begin.rst 189B
.place_design.begin.rst 189B
.init_design.begin.rst 189B
.vivado.begin.rst 189B
.vivado.begin.rst 188B
.vivado.begin.rst 188B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
.init_design.end.rst 0B
.Vivado_Implementation.queue.rst 0B
.vivado.end.rst 0B
.write_bitstream.end.rst 0B
共 222 条
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