/*
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_enet.h"
#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
#include "fsl_cache.h"
#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.enet"
#endif
/*! @brief IPv4 PTP message IP version offset. */
#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU
/*! @brief IPv4 PTP message UDP protocol offset. */
#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U
/*! @brief IPv4 PTP message UDP port offset. */
#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U
/*! @brief IPv4 PTP message UDP message type offset. */
#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU
/*! @brief IPv4 PTP message UDP version offset. */
#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU
/*! @brief IPv4 PTP message UDP clock id offset. */
#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU
/*! @brief IPv4 PTP message UDP sequence id offset. */
#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U
/*! @brief IPv4 PTP message UDP control offset. */
#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU
/*! @brief IPv6 PTP message UDP protocol offset. */
#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U
/*! @brief IPv6 PTP message UDP port offset. */
#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U
/*! @brief IPv6 PTP message UDP message type offset. */
#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU
/*! @brief IPv6 PTP message UDP version offset. */
#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU
/*! @brief IPv6 PTP message UDP clock id offset. */
#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U
/*! @brief IPv6 PTP message UDP sequence id offset. */
#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU
/*! @brief IPv6 PTP message UDP control offset. */
#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU
/*! @brief PTPv2 message Ethernet packet type offset. */
#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU
/*! @brief PTPv2 message Ethernet message type offset. */
#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU
/*! @brief PTPv2 message Ethernet version type offset. */
#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU
/*! @brief PTPv2 message Ethernet clock id offset. */
#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22
/*! @brief PTPv2 message Ethernet sequence id offset. */
#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c
/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */
#define ENET_ETHERNETL2 0x88F7U
/*! @brief Packet type IPv4. */
#define ENET_IPV4 0x0800U
/*! @brief Packet type IPv6. */
#define ENET_IPV6 0x86ddU
/*! @brief Packet type VLAN. */
#define ENET_8021QVLAN 0x8100U
/*! @brief UDP protocol type. */
#define ENET_UDPVERSION 0x0011U
/*! @brief Packet IP version IPv4. */
#define ENET_IPV4VERSION 0x0004U
/*! @brief Packet IP version IPv6. */
#define ENET_IPV6VERSION 0x0006U
/*! @brief Ethernet mac address length. */
#define ENET_FRAME_MACLEN 6U
/*! @brief Ethernet VLAN header length. */
#define ENET_FRAME_VLAN_TAGLEN 4U
/*! @brief MDC frequency. */
#define ENET_MDC_FREQUENCY 2500000U
/*! @brief NanoSecond in one second. */
#define ENET_NANOSECOND_ONE_SECOND 1000000000U
/*! @brief Define a common clock cycle delays used for time stamp capture. */
#ifndef ENET_1588TIME_DELAY_COUNT
#define ENET_1588TIME_DELAY_COUNT 10U
#endif
/*! @brief Defines the macro for converting constants from host byte order to network byte order. */
#define ENET_HTONS(n) __REV16(n)
#define ENET_HTONL(n) __REV(n)
#define ENET_NTOHS(n) __REV16(n)
#define ENET_NTOHL(n) __REV(n)
/*! @brief Define the ENET ring/class bumber . */
enum _enet_ring_number
{
kENET_Ring0 = 0U, /*!< ENET ring/class 0. */
#if FSL_FEATURE_ENET_QUEUE > 1
kENET_Ring1 = 1U, /*!< ENET ring/class 1. */
kENET_Ring2 = 2U /*!< ENET ring/class 2. */
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
};
/*! @brief Define interrupt IRQ handler. */
#if FSL_FEATURE_ENET_QUEUE > 1
typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
uint32_t ENET_GetInstance(ENET_Type *base);
/*!
* @brief Set ENET MAC controller with the configuration.
*
* @param base ENET peripheral base address.
* @param handle The ENET handle pointer.
* @param config ENET Mac configuration.
* @param bufferConfig ENET buffer configuration.
* @param macAddr ENET six-byte mac address.
* @param srcClock_Hz ENET module clock source, normally it's system clock.
*/
static void ENET_SetMacController(ENET_Type *base,
enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig,
uint8_t *macAddr,
uint32_t srcClock_Hz);
/*!
* @brief Set ENET handler.
*
* @param base ENET peripheral base address.
* @param handle The ENET handle pointer.
* @param config ENET configuration stucture pointer.
* @param bufferConfig ENET buffer configuration.
*/
static void ENET_SetHandler(ENET_Type *base,
enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig);
/*!
* @brief Set ENET MAC transmit buffer descriptors.
*
* @param handle The ENET handle pointer.
* @param config The ENET configuration structure.
* @param bufferConfig The ENET buffer configuration.
*/
static void ENET_SetTxBufferDescriptors(enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig);
/*!
* @brief Set ENET MAC receive buffer descriptors.
*
* @param handle The ENET handle pointer.
* @param config The ENET configuration structure.
* @param bufferConfig The ENET buffer configuration.
*/
static void ENET_SetRxBufferDescriptors(enet_handle_t *handle,
const enet_config_t *config,
const enet_buffer_config_t *bufferConfig);
/*!
* @brief Updates the ENET read buffer descriptors.
*
* @param base ENET peripheral base address.
* @param handle The ENET handle pointer.
* @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1.
* 0 ----- for single ring kinetis platform.
* 0 ~ 2 for mulit-ring supported IMX8qm.
*/
static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
/*!
* @brief Activates ENET send for multiple tx rings.
*
* @param base ENET peripheral base address.
* @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1.
* 0 ----- for single ring kinetis platform.
* 0 ~ 2 for mulit-ring supported IMX8qm.
*
* @note This must be called after the MAC configuration and
* state are ready. It must be called after the ENET_Init() and
* this should be called when the ENET receive required.
*/
static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId);
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
/*!
* @brief Parses the ENET frame for time-stamp process of PTP 1588 frame.
*
* @param data The ENE
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NXP i.MX RT1052实现uSDHC—SD卡读写测试
共1419个文件
h:674个
c:559个
scf:33个
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NXP i.MX RT1052实现uSDHC—SD卡读写测试 (1419个子文件)
fsl_enet.c 125KB
fsl_enet.c 113KB
fsl_enet.c 110KB
fsl_enet.c 110KB
fsl_enet.c 110KB
fsl_lpuart_cmsis.c 106KB
fsl_sai.c 105KB
fsl_lpuart_cmsis.c 104KB
fsl_lpuart_cmsis.c 103KB
fsl_lpuart_cmsis.c 103KB
fsl_lpuart_cmsis.c 103KB
fsl_flexcan.c 95KB
fsl_mmc.c 91KB
fsl_mmc.c 89KB
fsl_mmc.c 89KB
fsl_mmc.c 89KB
fsl_mmc.c 88KB
fsl_edma.c 87KB
fsl_edma.c 74KB
fsl_lpi2c.c 74KB
fsl_flexcan.c 73KB
fsl_edma.c 72KB
fsl_edma.c 72KB
fsl_edma.c 72KB
fsl_trng.c 72KB
fsl_lpuart.c 71KB
fsl_trng.c 71KB
fsl_flexcan.c 71KB
fsl_flexcan.c 71KB
fsl_flexcan.c 71KB
fsl_lpi2c_cmsis.c 70KB
fsl_trng.c 70KB
fsl_trng.c 70KB
fsl_trng.c 70KB
fsl_lpspi_cmsis.c 70KB
fsl_lpi2c_cmsis.c 69KB
fsl_lpspi.c 69KB
fsl_lpi2c_cmsis.c 68KB
fsl_lpi2c_cmsis.c 68KB
fsl_lpi2c_cmsis.c 68KB
fsl_lpspi_cmsis.c 68KB
fsl_usdhc.c 68KB
fsl_lpspi_cmsis.c 68KB
fsl_lpspi_cmsis.c 68KB
fsl_lpspi_cmsis.c 68KB
fsl_sai.c 66KB
fsl_sd.c 64KB
fsl_sai.c 64KB
fsl_sai.c 64KB
fsl_sai.c 64KB
fsl_usdhc.c 63KB
fsl_usdhc.c 61KB
fsl_usdhc.c 61KB
fsl_usdhc.c 61KB
fsl_lpspi.c 60KB
fsl_lpi2c.c 60KB
fsl_lpuart.c 58KB
fsl_lpspi.c 58KB
fsl_lpspi.c 58KB
fsl_lpspi.c 58KB
fsl_sd.c 58KB
fsl_lpi2c.c 58KB
fsl_lpi2c.c 58KB
fsl_lpi2c.c 58KB
fsl_lpuart.c 57KB
fsl_lpuart.c 57KB
fsl_lpuart.c 57KB
fsl_sd.c 56KB
fsl_sd.c 56KB
fsl_sd.c 56KB
startup_mimxrt1052.c 53KB
startup_mimxrt1052.c 52KB
startup_mimxrt1052.c 52KB
startup_mimxrt1052.c 52KB
startup_mimxrt1052.c 52KB
serial_manager.c 44KB
usb_device_ch9.c 43KB
fsl_str.c 43KB
fsl_dcp.c 42KB
fsl_str.c 42KB
fsl_str.c 42KB
fsl_str.c 42KB
fsl_str.c 42KB
fsl_flexio_spi.c 42KB
fsl_lpspi_edma.c 39KB
fsl_csi.c 39KB
fsl_semc.c 37KB
fsl_clock.c 37KB
fsl_lpspi_edma.c 37KB
fsl_semc.c 36KB
fsl_shell.c 36KB
fsl_sdio.c 36KB
fsl_dcp.c 36KB
fsl_lpspi_edma.c 36KB
fsl_lpspi_edma.c 36KB
fsl_lpspi_edma.c 36KB
fsl_sdio.c 35KB
fsl_flexio_i2c_master.c 35KB
fsl_semc.c 35KB
fsl_semc.c 35KB
共 1419 条
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