LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ligth IS
PORT(
CLK :in std_logic;
deng: out std_logic_vector(5 downto 0)
);END;
ARCHITECTURE ONE OF ligth is
TYPE state is (st0,st1,st2,st3,st4,st5,st6);
signal now_state: state:=st0;
signal clkout: std_logic:='0';
begin
com: process(clk)
variable output1 : INTEGER range 0 to 999;
begin
if clk'event and clk='1' then
if output1<999 then output1:=output1+1; clkout<='0';
else output1:=0; clkout<='1';
end if;
end if;
end process;
reg:process(clkout)
variable adder: INTEGER range 0 to 49;
begin
if clkout'EVENT AND clkout='1' then
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