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### NCN6001接口芯片相关知识点 #### 一、概述 NCN6001是一款紧凑型智能卡接口集成电路（IC），该芯片专为智能卡接口应用设计。它支持ISO7816-3、EMV以及GIE-CB等标准，能够处理各种类型的智能卡，并通过简单的微控制器接口进行操作。此外，该设备内置了芯片选择逻辑，允许并行耦合操作，特别适合于低成本、低功耗的应用场景。 #### 二、特点与优势 1. **兼容性**：100%兼容ISO7816-3、EMV和GIE-CB标准，完全符合GSM规范。 2. **宽电源电压范围**：支持2.7V至5.5V的电池供电电压范围。 3. **可编程CRD_VCC电源**：可以配置为1.8V、3.0V或5.0V，以满足不同智能卡的工作需求。 4. **可编程时钟特性**： - 可编程上升和下降沿的卡片时钟斜率。 - 可编程卡片时钟分频器。 - 内置的可编程CRD_CLK停止功能，支持运行状态或低电平状态。 - 可编程CRD_CLK斜率，应对广泛的操作频率范围。 5. **并行耦合能力**：内置的芯片选择逻辑使得多个耦合器可以并行连接。 6. **ESD保护**：卡片引脚上的静电放电（ESD）保护，最高可达8.0kV（人体模型）。 7. **高速操作**：支持高达40MHz的输入时钟频率。 8. **快速CRD_VCC开关序列**：提供快速的CRD_VCC开启和关闭序列。 9. **低功耗设计**：具有极低的静态电流，适用于延长电池寿命的应用场景。 #### 三、典型应用领域 1. **电子商务接口**：用于在线支付系统中的智能卡认证。 2. **自动取款机（ATM）智能卡**：在银行和金融机构中用于身份验证和交易授权。 3. **销售点（POS）系统**：在零售业中用于支付处理和客户信息管理。 4. **付费电视系统**：用于数字内容保护和访问控制。 #### 四、技术细节 1. **封装形式**：采用TSSOP-20封装形式，支持2500个/卷的带状包装。 2. **引脚定义**： - CLK_SPI：SPI时钟引脚。 - I/O：通用输入/输出引脚。 - INT：中断输出引脚。 - CLK_IN：外部时钟输入引脚。 - MOSI：主出从入数据引脚。 - EN_RPU：上拉电阻使能引脚。 - MISO：主入从出数据引脚。 - CS：芯片选择引脚。 - Lout_H/Lout_L：输出驱动器高/低电平引脚。 - GND：接地引脚。 - CRD_VCC：智能卡电源引脚。 - CRD_CLK：智能卡时钟引脚。 - CRD_IO：智能卡数据输入/输出引脚。 - VCC：电源引脚。 - PWR_GND：电源地引脚。 - CRD_RST：智能卡复位引脚。 - CRD_DET：智能卡检测引脚。 - C8/S1/C4/S0：配置引脚。 3. **无铅设计**：NCN6001为无铅产品，符合环保要求。 #### 五、总结 NCN6001作为一款专为智能卡接口设计的集成电路，不仅提供了广泛的兼容性和灵活性，还具备出色的低功耗性能。其独特的并行耦合能力和内置的多种可编程功能使其成为多种应用场景的理想选择，特别是在需要低成本、低功耗解决方案的情况下。对于那些需要高效、稳定且易于集成智能卡接口的项目来说，NCN6001无疑是一个极具吸引力的选择。

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January, 2006 − Rev. 3

1 Publication Order Number:

NCN6001/D

NCN6001

Compact Smart Card

Interface IC

The NCN6001 is an integrated circuit dedicated to the smart card

interface applications. The device handles any type of smart card

through a simple and flexible microcontroller interface. On top of that,

thanks to the built−in chip select pin, several couplers can be

connected in parallel.

The device is particularly suited for low cost, low power

applications, with high extended battery life coming from extremely

low quiescent current.

Features

• 100% Compatible with ISO 7816−3, EMV and GIE−CB Standards

• Fully GSM Compliant

• Wide Battery Supply Voltage Range: 2.7 < V

< 5.5 V

• Programmable CRD_VCC Supply Handles 1.8 V, 3.0 V or 5.0 V

Card Operation

• Programmable Rise and Fall Card Clock Slopes

• Programmable Card Clock Divider

• Built−in Chip Select Logic Allows Parallel Coupling Operation

• ESD Protection on Card Pins (8.0 kV, Human Body Model)

• Supports up to 40 MHz Input Clock

• Built−in Programmable CRD_CLK Stop Function Handles Run or

Low State

• Programmable CRD_CLK Slopes to Cope with Wide Operating

Frequency Range

• Fast CRD_VCC Turn−on and Turn−off Sequence

• These are Pb−Free Devices*

Typical Applications

• E−Commerce Interface

• Automatic Teller Machine (ATM) Smart Card

• Point of Sales (POS) System

• Pay TV System

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Device Package Shipping

†

ORDERING INFORMATION

NCN6001DTBR2 TSSOP−20* 2500 Tape & Ree

TSSOP−20

DTB SUFFIX

CASE 948E

MARKING DIAGRAM

PIN CONNECTIONS

(Top View)

CLK_SPI

I/O

INT

CLK_IN

MOSI

EN_RPU

MISO

Lout_H

GND

CRD_VCC

CRD_CLK

CRD_IO

10 11

Lout_L PWR_GND

CRD_RST

CRD_DET

C8/S1

C4/S0

http://onsemi.com

NCN6001DTBR2G TSSOP−20* 2500 Tape & Ree

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

*This package is inherently Pb−Free.

NCN

6001

ALYWG

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

(Note: Microdot may be in either location)

NCN6001

http://onsemi.com

PIN FUNCTIONS AND DESCRIPTION

Pin Name Type Description

1 I/O Input/Output

Pullup

This pin is connected to an external microcontroller interface. A bidirectional level

translator adapts the serial I/O signal between the smart card and the microcontroller.

The level translator is enabled when CS = L, the sub address has been selected and the

system operates in the Asynchronous mode. When a Synchronous card is in use, this pin

is disconnected and the data and the transaction take place with the MISO b3 register.

The internal pullup resistor connected on the C side is activated and visible by the

selected chip only.

2 INT OUTPUT

Pullup

This pin is activated LOW when a card has been inserted and detected by CRD_DET pin.

Similarly, an interrupt is generated when the CRD_VCC output is overloaded, or when

the card has been extracted whatever be the transaction status (running or standby).

The INT signal is reset to High according to Table 7 and Figure 11. On the other hand, the

pin is forced to a logic High when the input voltage V

drops below 2.0 V.

3 CLK_IN CLOCK INPUT

High impedance

The built−in Schmitt trigger receiver makes this pin suitable for a large type of clock

signal (Figure 30). This pin can be connected to either the microcontroller master clock,

or to a crystal signal, to drive the external smart cards. The signal is fed to the internal

clock selector circuit and translated to the CRD_CLK pin at either the same frequency, or

divided by 2 or 4, depending upon the programming mode.

Note: The chip guarantees the EMV 50% Duty Cycle when the clock divider ratio is 1/2 or

1/4, even when the CLK_IN signal is out of the 45% to 55% range specified by ISO and

EMV specifications.

Care must be observed, at PCB level, to minimize the pick−up noise coming from the

CLK_IN line.

4 MOSI INPUT Master Out Slave In: SPI Data Input from the external microcontroller. This byte contents

the address of the selected chip among the four possible, together with the programming

code for a given interface.

5 CLK_SPI INPUT Clock Signal to synchronize the SPI data transfer. The built−in Schmitt trigger receiver

makes this pin compatible with a wide range of input clock signal (Figure 30). This clock

is fully independent from the CLK_IN signal and does not play any role with the data

transaction.

6 EN_RPU INPUT, Logic This pin is used to activate the I/O internal pullup resistor according to the here below

true table:

EN_RPU = Low → I/O Pullup resistor disconnected

EN_RPU = High → I/O Pullup resistor connected

When two or more NCN6001 chips shares the same I/O bus, one chip only shall have the

internal pullup resistor enabled to avoid any overload of the I/O line.

Moreover, when Asynchronous and Synchronous cards are handled by the interfaces,

the activated I/O pullup resistor must preferably be the one associated with the

Asynchronous circuit.

On the other hand, since no internal pullup bias resistor is built in the chip, pin 6 must be

connected to the right voltage level to make sure the logic function is satisfied.

7 MISO OUTPUT Master In Slave Out: SPI Data Output from the NCN6001. This byte carries the state of

the interface, the serial transfer being achieved according to the programmed mode

(Table 2), using the same CLK_SPI signal and during the same MOSI time frame. The

three high bits [b7:b5] have no meaning and shall be discarded by the microcontroller. An

external 4.7 k Pull down resistor might be necessary to avoid misunderstanding of the

pin 7 voltage during the High Z state.

8 CS INPUT This pin synchronizes the SPI communication and provides the chip address and

selected functions.

All the NCN6001 functions, both programming and card transaction, are disabled when

CS = H.

9 V

POWER This pin is connected to the NCN6001 supply voltage and must be bypassed to ground

by a 10 F/6.0 V capacitor.

Since tantalum capacitors have relative high ESR, using low ESR ceramic type

(MURATA X5R, Resr < 100 m) is highly recommended.

10 Lout_H POWER The High Side of the external inductor is connected between this pin and Lout_L/pin 12 to

provide the DC/DC function. The current flowing into this inductor is internally sensed and

no external shunt resistor is used. Typically, Lout = 22 H, with ESR < 2.0 , yields a

good efficiency performance for a maximum 65 mA DC output load.

Note: The inductor shall be sized to handle the 450 mA peak current flowing during the

DC/DC operation (see CoilCraft manufacturer data sheet).

NCN6001

http://onsemi.com

PIN FUNCTIONS AND DESCRIPTION

Pin DescriptionTypeName

11 PWR_GND POWER This pin is the Power Ground associated with the built−in DC/DC converter and must be

connected to the system ground together with GROUND pin 16. Using good quality

ground plane is recommended to avoid spikes on the logic signal lines.

12 Lout_L POWER The High Side of the external inductor is connected between this pin and Lout_H to

activate the DC/DC function. The built−in NMOS and PMOS devices provide the

switching function together with the CRD_VCC voltage rectification (Figure 17).

13 CRD_VCC POWER This pin provides the power to the external card. It is the logic level “1” for CRD_IO,

CRD_RST, CRD_C4, CRD_C8 and CRD_CLK signals.

The energy stored by the DC/DC external inductor Lout must be smoothed by a

10 F/Low ESR capacitor, connected across CRD_VCC and GND. Using ceramic type of

capacitor (MURATA X5R, ESR < 50 m) is strongly recommended. In the event of a

CRD_VCC U

VLOW

voltage, the NCN6001 detects the situation and feedback the

information in the STATUS bit. The device does not take any further action, particularly

the DC/DC converter is neither stopped nor re programmed by the NCN6001. It is up to

the external MPU to handle the situation.

However, when the CRD_VCC is overloaded, the NCN6001 shuts off the DC/DC

converter, runs a Power Down ISO sequence and reports the fault in the STATUS

Since high transient current flows from this pin to the load, care must be observed, at

PCB level, to minimize the series ESR and ESL parasitic values. The NCN6001 demo

board provides an example of a preferred PCB layout.

14 C8/S0 I/O Auxiliary mixed analog/digital line to handle either a synchronous card, or as Chip Select

Identification (MISO, Bit 0): see Figure 9. The pin is driven by an open drain stage, the

pullup resistor being connected to the CRD_VCC supply. When the pin is used as a logic

input (asynchronous cards), the positive logic condition applies:

Connected to GND → Logic = Zero

Connected to V

or left Open → Logic = One

A built−in accelerator circuit makes sure the output positive going rise time is fully within

the ISO/EMV specifications.

NOTE: The pin is capable of reading the logic level when the chip operates an

asynchronous interface, but is not intended to read the data from the external

card when operated in the synchronous mode. It merely returns the logic state

forced during a write instruction to the card.

15 C4/S1 I/O Auxiliary mixed analog/digital line to handle either a synchronous card, or as Chip Select

Identification (MISO, Bit 1): see Figure 9. The pin is driven by an open drain stage, the

pullup resistor being connected to the CRD_VCC supply. When the pin is used as a logic

input (asynchronous cards), the positive logic condition applies:

Connected to GND → Logic = Zero

Connected to V

or left Open → Logic = One

A built−in accelerator circuit makes sure the output positive going rise time is fully within

the ISO/EMV specifications.

NOTE: The pin is capable of reading the logic level when the chip operates an

asynchronous interface, but is not intended to read the data from the external

card when operated in the synchronous mode. It merely returns the logic state

forced during a write instruction to the card.

16 GROUND SIGNAL The logic and low level analog signals shall be connected to this ground pin. This pin

must be externally connected to the PWR_GND pin 12. The designer must make sure no

high current transients are shared with the low signal currents flowing into this pin.

17 CRD_CLK OUTPUT This pin is connected to the CLK pin of the card connector. The CRD_CLK signal comes

from the clock selector circuit output. An internal active pull down NMOS device forces this

pin to Ground during either the CRD_VCC startup sequence, or when CRD_VCC = 0 V.

The rise and fall slopes, either FAST or SLOW, of this signal can be programmed by the

MOSI message (Table 2).

Care must be observed, at PCB level, to minimize the pick−up noise coming from the

CRD_CLK line.

NCN6001

http://onsemi.com

PIN FUNCTIONS AND DESCRIPTION

Pin DescriptionTypeName

18 CRD_DET INPUT The signal coming from the external card connector is used to detect the presence of the

card. A built−in pullup low current source biases this pin High, making it active LOW,

assuming one side of the external switch is connected to ground. A built−in digital filter

protect the system against voltage spikes present on this pin.

The polarity of the signal is programmable by the MOSI message, according to the logic

state depicted Table 2. On the other hand, the meaning of the feedback message

contained in the MISO register bit b4, depends upon the SPI mode of operation as

defined here below:

SPI Normal Mode: The MISO bit b4 is High when a card is inserted, whatever be the

polarity of the card detect switch.

SPI Special Mode: The MISO bit b4 copies the logic state of the Card detect switch as

depicted here below, whatever be the polarity of the switch used to handle the detection:

CRD_DET = Low → MISO/b4 = Low

CRD_DET = High → MISO/b4 = High

In both cases, the chip must be programmed to control the right logic state (Table 2).

Since the bias current supplied by the chip is very low, typically 5.0 A, care must be

observed to avoid low impedance or cross coupling when this pin is in the Open state.

19 CRD_RST OUTPUT This pin is connected to the RESET pin of the card connector. A level translator adapts

the RESET signal from the microcontroller to the external card. The output current is

internally limited to 15 mA.

The CRD_RST is validated when CS = Low and hard wired to Ground when the card is

deactivated, by and internal active pull down circuit.

Care must be observed, at PCB design level, to avoid cross coupling between this signal

and the CRD_CLK clock.

20 CRD_IO I/O

Pullup

This pin handles the connection to the serial I/O pin of the card connector. A bidirectional

level translator adapts the serial I/O signal between the card and the microcontroller. An

internal active pull down MOS device forces this pin to Ground during either the

CRD_VCC startup sequence, or when CRD_VCC = 0 V. The CRD_IO pin current is

internally limited to 15 mA.

Care must be observed, at PCB design level, to avoid cross coupling between this signal

and the CRD_CLK clock.

剩余33页未读，继续阅读

评论收藏

内容反馈

zhengchengqi

2013-01-08

是啊，很可惜呢，希望有人上传中文版
BexTan

2012-04-26

很好，正用得上，英文资料无错
woshi_ziyu

2014-10-15

英文版本和官方下载的一样
smileta

2012-03-28

可惜不是中文的
qust_huangdong

2012-11-26

可惜不是中文版的

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