SAA7121_初始化verilog代码

module my_I2C(SDA,SCL,ACK,RESET,CLK,WR,div_clk,saa7121_llc,flag);

output SCL;
inout SDA;
input ACK;   //定义了原理图文件，给了一个应答，无关紧要可以不要
output RESET;
output WR;
output div_clk;
output saa7121_llc;
output flag;//应答的标志变化信号，其实可以不等待应答
input CLK;

wire div_clk;
wire saa7121_llc;

wire ACK;
reg flag;
reg SCL;
reg SDA;
reg CLK2;
reg RESET;
reg WR;
reg [2:0] start_count;
reg [4:0] send_count;
reg [4:0] send_count2;
reg [6:0] send_count3;
reg [2:0] stop_count;
reg [1:0] stop_state;
reg [1:0] start_state;
reg [3:0] send_state;

reg [3:0] main_state;
reg [7:0] addr_data;
reg [7:0] data;
reg [7:0] slave_data;

reg [7:0] sub_data[45:0];
reg [7:0] mem[45:0];
reg [11:0] count1;
reg [7:0] i;

initial    //初始化
begin
 main_state      = 4'b0000;
 SDA       = 1'b1;
 SCL       = 1'b1;
 start_count     = 3'b000;
 send_count     = 4'b0000;
 send_count2     = 5'b00000;
 send_count3     = 7'b0000000;
 stop_count     = 3'b000;
 start_state     = 2'b00;
 stop_state      = 2'b00;
 send_state     = 4'b000;
 count1         = 12'h0;
 slave_data  = 8'b10001000;
 data       = 8'b10101010;
 WR              = 1'b1;
 RESET           = 1'b1;
 i               = 8'b00000000;
 sub_data[0]     = 8'h26;//sub_data是从器件地址