//////////////////////////////////////////////////////////////////////
//// ////
//// README.txt ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: README.txt,v $
// Revision 1.1 2002/09/18 16:50:08 mohor
// Several information added to the file.
//
//
//
//
RUNNING the simulation/Testbench in ModelSIM:
Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
Run the macro do.do (write "do do.do" in the command window).
Simulation will be automatically started. Logs are stored in the /log
directory. tb_ethernet test is performed.
RUNNING the simulation/Testbench in Ncsim:
Go to the ethernet\sim\rtl_sim\ncsim_sim\run directory. Run the
run_eth_sim_regr.scr script. Simulation is automatically started. Logs are
stored in the /log directory. Before running the script for another time,
run the clean script that deletes files from previous runs. tb_ethernet test
is performed.
Why are eth_cop.v, eth_host.v, eth_memory, tb_cop.v and tb_ethernet_with_cop.v
files used for?
Although the testbench does not include the traffic coprocessor, the
coprocessor is part of the ethernet environment. eth_cop multiplexes
two wishbone interface between 4 modules:
- First wishbone master interface is connected to the HOST (eth_host)
- Second wishbone master interface is connected to the Ethernet Core (for
accessing data in the memory (eth_memory)).
- First wishbone slave interface is connected to the Ethernet Core (for
accessing registers and buffer descriptors).
- Second wishbone slave interface is connected to the memory (eth_memory)
so host can write data to the memory (or read data from the memory.
tb_cop.c is a testbench just for the traffic coprocessor (eth_cop).
tb_ethernet_with_cop.v is a simple testbench where all above mentioned
modules are connected into a single environment. Few packets are transmitted
and received. The "main" testbench is tb_ethernet.v file. It performs several
tests (eth_cop is not part of the simulation environment).
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Ethernet controller RTL code
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Ethernet controller RTL code (223个子文件)
_info 57B
ncelab_xilinx.args 201B
ncelab_xilinx.args 201B
ncelab.args 154B
ncelab.args 154B
BUGS 3KB
clean 101B
clean 101B
dir_keeper 0B
dir_keeper 0B
dir_keeper 0B
dir_keeper 0B
dir_keeper 0B
dir_keeper 0B
top_groups.do 16KB
eth_wave.do 11KB
top_groups.do 9KB
tb_eth.do 7KB
do.do 3KB
eth_speci.doc 554KB
eth_design_document.doc 417KB
ethernet_datasheet_OC_head.doc 171KB
ethernet_product_brief_OC_head.doc 154KB
Entries 1KB
Entries 687B
Entries 533B
Entries 524B
Entries 252B
Entries 252B
Entries 175B
Entries 143B
Entries 143B
Entries 143B
Entries 93B
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Entries 3B
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Entries 3B
Entries 3B
Entries 3B
Entries 3B
Entries 3B
Entries 3B
dir.keeper 0B
dir.keeper 0B
dir.keeper 0B
dir.keeper 0B
cds.lib 89B
cds.lib 89B
eth_tb.log 340KB
tb_eth_display.log 95KB
Entries.Log 93B
Entries.Log 54B
Entries.Log 52B
Entries.Log 52B
Entries.Log 19B
Entries.Log 19B
Entries.Log 17B
Entries.Log 17B
Entries.Log 17B
Entries.Log 17B
Entries.Log 17B
Entries.Log 14B
Entries.Log 13B
rtl_file_list.lst 1009B
rtl_file_list.lst 980B
sim_file_list.lst 527B
sim_file_list.lst 349B
xilinx_file_list.lst 210B
artisan_file_list.lst 206B
xilinx_file_list.lst 199B
artisan_file_list.lst 143B
vs_file_list.lst 67B
ethernet.mpf 21KB
vlog.opt 68B
eth_speci.pdf 248KB
eth_design_document.pdf 159KB
ethernet_datasheet_OC_head.pdf 20KB
ethernet_product_brief_OC_head.pdf 19KB
ncsim_waves.rc 158B
ncsim_waves.rc 158B
ncsim.rc 11B
ncsim.rc 11B
Repository 54B
Repository 46B
Repository 44B
Repository 44B
Repository 39B
Repository 39B
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Repository 36B
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