arm.rar_ARMIP核_armRTLcode_armrtl_armverilog

共45个文件

vhd：41个

bak：1个

h：1个

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95 浏览量 2022-09-14 16:08:09 上传评论收藏 74KB RAR 举报

ARM IP核是嵌入式系统设计中的核心组件，它代表了Advanced RISC Machines（ARM）公司的微处理器架构。在本“arm.rar”压缩包中，包含的资源主要涉及ARM IP核的RTL（Register Transfer Level）代码，这是一类用于描述数字逻辑电路行为的高级语言，如Verilog和VHDL。RTL代码是硬件描述语言（HDL）的一种，常用于数字集成电路的设计，特别是在FPGA（Field-Programmable Gate Array）和ASIC（Application-Specific Integrated Circuit）的开发中。让我们深入了解ARM IP核。ARM IP核是由ARM公司提供的可授权技术，它包括一系列不同性能和功耗级别的处理器内核，比如Cortex-A、Cortex-R和Cortex-M系列。这些内核被广泛应用于移动设备、物联网设备、服务器、嵌入式系统等各个领域。用户可以根据自身需求选择合适的IP核，并将其集成到自己的SoC（System on Chip）设计中。描述中提到的“arm vhdl rtl code, can synthesis”表明，这个压缩包包含了可以进行综合的ARM处理器的VHDL（VHSIC Hardware Description Language）RTL代码。VHDL是一种标准的HDL，用于描述数字系统的结构和行为。通过这种代码，设计者能够精确地表达硬件电路的行为，然后使用EDA（Electronic Design Automation）工具进行逻辑综合，将RTL代码转换成门级网表，进而实现硬件的物理布局和布线。在实际设计过程中，使用VHDL编写ARM IP核的RTL代码可以让设计者在高层次上描述处理器的逻辑功能，而不必关心具体的电路实现细节。这样的代码可以被综合工具理解，生成对应的门级模型，从而在FPGA或ASIC上实现。这对于快速原型验证和硬件定制是非常有价值的。 “arm_rtl_code”指的是ARM处理器的RTL描述，它通常包括处理器的控制单元、算术逻辑单元（ALU）、寄存器文件、总线接口等组件的详细逻辑表示。RTL代码的质量和优化程度直接影响到最终硬件的性能、面积和功耗。至于“arm_verilog”，这是另一种常用的HDL，与VHDL类似，用于描述数字系统。Verilog更侧重于过程和事件驱动的编程风格，而VHDL则更注重数据结构和并行处理。不过，两者在现代设计中都得到了广泛应用，可以互相转换，以满足不同设计团队的需求。这个“arm.rar”压缩包提供的是基于ARM架构的IP核的RTL代码，包括VHDL和可能的Verilog版本。这些代码可用于FPGA或ASIC的实现，经过综合工具处理后，能够转化为实际的硬件电路。对于电子设计工程师来说，掌握和利用这些资源能够加速他们的设计流程，提高产品的创新性和竞争力。

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arm.rar （45个子文件）

arm

armiu_exstg.vhd 23KB

armiu_drstg.vhd 51KB

armcmd_cr.vhd 4KB

arm_comp.vhd 13KB

c_model

arm.c 37KB

arm.h 1B

armiu_destg.vhd 5KB

armiu_wrstg.vhd 10KB

armcmd_bl.vhd 4KB

armcache.vhd 4KB

armcmd_comp.vhd 7KB

armcmd_cl.vhd 9KB

armcmd_lm.vhd 10KB

armcp_sctrl.vhd 9KB

armcp_comp.vhd 339B

libs

armsctrl.vhd 1KB

armcoproc.vhd 7KB

armcmd_cs.vhd 2KB

armiu_rrstg.vhd 9KB

armcmd_sm.vhd 11KB

armiu_festg.vhd 3KB

armiu_dmstg.vhd 2KB

armiu_rsstg.vhd 4KB

arm_proc.vhd 2KB

tbench_armcache.vhd 13KB

armiu.vhd 15KB

armiu_imstg.vhd 2KB

armcmd_al.vhd 7KB

armcmd_st.vhd 11KB

config.in 226B

armcmd_sr.vhd 5KB

armcmd_ld.vhd 9KB

armcmd_sw.vhd 8KB

libs

armcmd_iface.vhd 1B

armcmd.vhd.bak 10KB

armdebug.vhd 3KB

armdecode.vhd 42KB

armldst.vhd 8KB

armctrl.vhd 9KB

armpctrl.vhd 17KB

armiu_iface.vhd 1B

armshiefter.vhd 17KB

armcmd.vhd 10KB

armpmodel.vhd 12KB

armiu_mestg.vhd 4KB

typedef struct _proc_state {} proc_state; typedef struct _insn_dp_i_s_struct { /*Data Processing immidiate shieft*/ int (*func) (struct _insn_dp_i_s_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int op1: 5; /*Data processing opcode*/ unsigned int dps: 2; /*Update cpsr*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int sha: 6; /*Shieft amount*/ unsigned int sh: 3; /*Shieft direction*/ unsigned int rm: 5; /*Register rm*/ } insn_dp_i_s_struct; typedef struct _insn_msr_struct { /*Move status register to register*/ int (*func) (struct _insn_msr_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int R: 2; /*Cpsr|Spsr '1'=Spsr*/ unsigned int SBO: 5; /**/ unsigned int rd: 5; /*Destination register rd*/ unsigned int SBZ: 5; /**/ unsigned int SBZ2: 5; /**/ } insn_msr_struct; typedef struct _insn_mrs_struct { /*Move register to status register*/ int (*func) (struct _insn_mrs_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int R: 2; /*Cpsr|Spsr '1'=Spsr*/ unsigned int msk: 5; /**/ unsigned int SBO: 5; /**/ unsigned int SBZ: 5; /**/ unsigned int rm: 5; /*Register rm*/ } insn_mrs_struct; typedef struct _insn_bex_struct { /*Branch / exchange*/ int (*func) (struct _insn_bex_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int SBO: 13; /**/ unsigned int rm: 5; /*Register rm*/ } insn_bex_struct; typedef struct _insn_clz_struct { /*Count leading zero*/ int (*func) (struct _insn_clz_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int SBO: 5; /**/ unsigned int rd: 5; /*Destination register rd*/ unsigned int SBO2: 5; /**/ unsigned int rm: 5; /*Register rm*/ } insn_clz_struct; typedef struct _insn_blx_struct { /*Branch and link /exchange*/ int (*func) (struct _insn_blx_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int SBO: 13; /**/ unsigned int rm: 5; /*Register rm*/ } insn_blx_struct; typedef struct _insn_dsa_struct { /*Dsp add|sub*/ int (*func) (struct _insn_dsa_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int dsop: 3; /*Dsp operand*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int SBZ: 5; /**/ unsigned int rm: 5; /*Register rm*/ } insn_dsa_struct; typedef struct _insn_brk_struct { /*Breakpoint*/ int (*func) (struct _insn_brk_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int imm: 13; /*Breakpoint imm part1*/ unsigned int imm2: 5; /*Breakpoint imm part2*/ } insn_brk_struct; typedef struct _insn_dsm_struct { /*DSP multiply*/ int (*func) (struct _insn_dsm_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int dsop: 3; /*Dsp operand*/ unsigned int RD: 5; /**/ unsigned int rn: 5; /*Register rn*/ unsigned int rs: 5; /*Register rs*/ unsigned int y: 2; /**/ unsigned int x: 2; /**/ unsigned int rm: 5; /*Register rm*/ } insn_dsm_struct; typedef struct _insn_dp_r_s_struct { /*Data processing register shieft*/ int (*func) (struct _insn_dp_r_s_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int op1: 5; /*Data processing opcode*/ unsigned int dps: 2; /*Update cpsr*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int rs: 5; /*Register rs*/ unsigned int sh: 3; /*Shieft direction*/ unsigned int rm: 5; /*Register rm*/ } insn_dp_r_s_struct; typedef struct _insn_mula_struct { /*Multiply and accumulate*/ int (*func) (struct _insn_mula_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int MA: 2; /*Multiply accumulate*/ unsigned int MS: 2; /*Set cpsr*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int rn: 5; /*Register rn*/ unsigned int rs: 5; /*Register rs*/ unsigned int rm: 5; /*Register rm*/ } insn_mula_struct; typedef struct _insn_mull_struct { /*Multiply long*/ int (*func) (struct _insn_mull_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int MU: 2; /*Multiply unsigned*/ unsigned int MA: 2; /*Multiply accumulate*/ unsigned int MS: 2; /*Set cpsr*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int rdl: 5; /*Destination register long*/ unsigned int rs: 5; /*Register rs*/ unsigned int rm: 5; /*Register rm*/ } insn_mull_struct; typedef struct _insn_swp_struct { /*Swap|swap byte*/ int (*func) (struct _insn_swp_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int SB: 2; /*Swap byte*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int sbz: 5; /**/ unsigned int rm: 5; /*Register rm*/ } insn_swp_struct; typedef struct _insn_ld1_struct { /*Load|Store halfword*/ int (*func) (struct _insn_ld1_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int LSP: 2; /*pre-indexed*/ unsigned int LSU: 2; /*add/sub base '1'=add*/ unsigned int LSW: 2; /*writeback*/ unsigned int LSL: 2; /*Load|Store '1'=Load*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int sbz: 5; /**/ unsigned int rm: 5; /*Register rm*/ } insn_ld1_struct; typedef struct _insn_ld2_struct { /*Load|Store halfword immidiate offset*/ int (*func) (struct _insn_ld2_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int LSP: 2; /*pre-indexed*/ unsigned int LSU: 2; /*add/sub base '1'=add*/ unsigned int LSW: 2; /*writeback*/ unsigned int LSL: 2; /*Load|Store '1'=Load*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int i81: 5; /*Immidiate8 part1*/ unsigned int i82: 5; /*Immidiate8 part2*/ } insn_ld2_struct; typedef struct _insn_ld3_struct { /*Load|Store two words register offset*/ int (*func) (struct _insn_ld3_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int LSP: 2; /*pre-indexed*/ unsigned int LSU: 2; /*add/sub base '1'=add*/ unsigned int LSW: 2; /*writeback*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int i81: 5; /*Immidiate8 part1*/ unsigned int S: 2; /*Signed|Unsigned '1'=signed*/ unsigned int i82: 5; /*Immidiate8 part2*/ } insn_ld3_struct; typedef struct _insn_ld4_struct { /*Load|Store signed halfword/byte register offset*/ int (*func) (struct _insn_ld4_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int LSP: 2; /*pre-indexed*/ unsigned int LSU: 2; /*add/sub base '1'=add*/ unsigned int LSW: 2; /*writeback*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int i81: 5; /*Immidiate8 part1*/ unsigned int H: 2; /*halfword|signedbyte '1'=halfword*/ unsigned int i82: 5; /*Immidiate8 part2*/ } insn_ld4_struct; typedef struct _insn_ld5_struct { /*Load|Store two words register offset*/ int (*func) (struct _insn_ld5_struct *s, proc_state *state); unsigned int c: 5; /*Condition code*/ unsigned int LSP: 2; /*pre-indexed*/ unsigned int LSU: 2; /*add/sub base '1'=add*/ unsigned int LSW: 2; /*writeback*/ unsigned int rn: 5; /*Register rn*/ unsigned int rd: 5; /*Destination register rd*/ unsigned int i81: 5; /*Immidiate8 part1*/ unsigned int S: 2; /*Signed|Unsigned '1'=signed*/ unsigned int i82: 5; /*Immidiate8 part2*/ } insn_ld5_struct; typedef struct _insn_ld6_struct { /*Load|Store signed halfword/byte immidiate offset*/ int (*func) (struct _insn_ld6_struct *s, proc_state *state); unsigned int c: 5; /*Condi