S3C2440 SD卡linux驱动程序

#include <linux/module.h> #include <linux/dma-mapping.h> #include <linux/clk.h> #include <linux/mmc/host.h> #include <linux/platform_device.h> #include <linux/cpufreq.h> #include <linux/debugfs.h> #include <linux/seq_file.h> #include <linux/gpio.h> #include <linux/irq.h> #include <linux/io.h> #include <mach/dma.h> #include <mach/regs-sdi.h> #include <mach/regs-gpio.h> #include <plat/mci.h> #define DRIVER_NAME "s3c-sd" enum s3cmci_waitfor { COMPLETION_NONE, COMPLETION_FINALIZE, COMPLETION_CMDSENT, COMPLETION_RSPFIN, COMPLETION_XFERFINISH, COMPLETION_XFERFINISH_RSPFIN, }; struct s3cmci_host { struct platform_device *pdev; struct s3c24xx_mci_pdata *pdata; struct mmc_host *mmc; struct resource *mem; struct clk *clk; void __iomem *base; int irq; int irq_cd; int dma; unsigned long clk_rate; unsigned long clk_div; unsigned long real_rate; u8 prescaler; int is2440; unsigned sdiimsk; unsigned sdidata; int dodma; int dmatogo; bool irq_disabled; bool irq_enabled; bool irq_state; int sdio_irqen; struct mmc_request *mrq; int cmd_is_stop; spinlock_t complete_lock; enum s3cmci_waitfor complete_what; int dma_complete; u32 pio_sgptr; u32 pio_bytes; u32 pio_count; u32 *pio_ptr; #define XFER_NONE 0 #define XFER_READ 1 #define XFER_WRITE 2 u32 pio_active; int bus_width; char dbgmsg_cmd[301]; char dbgmsg_dat[301]; char *status; unsigned int ccnt, dcnt; struct tasklet_struct pio_tasklet; #ifdef CONFIG_DEBUG_FS struct dentry *debug_root; struct dentry *debug_state; struct dentry *debug_regs; #endif #ifdef CONFIG_CPU_FREQ struct notifier_block freq_transition; #endif }; static struct resource s3c_sdi_resource[] = { [0] = { .start = S3C24XX_PA_SDI, .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1, .flags = IORESOURCE_MEM, }, [1] = { .start = IRQ_SDI, .end = IRQ_SDI, .flags = IORESOURCE_IRQ, } }; struct platform_device s3c_device_sdi = { .name = "sdi", .id = -1, .num_resources = ARRAY_SIZE(s3c_sdi_resource), .resource = s3c_sdi_resource, }; enum dbg_channels { dbg_err = (1 << 0), dbg_debug = (1 << 1), dbg_info = (1 << 2), dbg_irq = (1 << 3), dbg_sg = (1 << 4), dbg_dma = (1 << 5), dbg_pio = (1 << 6), dbg_fail = (1 << 7), dbg_conf = (1 << 8), }; static const int dbgmap_err = dbg_fail; static const int dbgmap_info = dbg_info | dbg_conf; static const int dbgmap_debug = dbg_err | dbg_debug; #define dbg(host, channels, args...) \ do { \ if (dbgmap_err & channels) \ dev_err(&host->pdev->dev, args); \ else if (dbgmap_info & channels) \ dev_info(&host->pdev->dev, args); \ else if (dbgmap_debug & channels) \ dev_dbg(&host->pdev->dev, args); \ } while (0) static struct s3c2410_dma_client s3cmci_dma_client = { .name = "s3c-mci", }; static void finalize_request(struct s3cmci_host *host); static void s3cmci_send_request(struct mmc_host *mmc); static void s3cmci_reset(struct s3cmci_host *host); #ifdef CONFIG_MMC_DEBUG static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize; u32 datcon, datcnt, datsta, fsta, imask; con = readl(host->base + S3C2410_SDICON); pre = readl(host->base + S3C2410_SDIPRE); cmdarg = readl(host->base + S3C2410_SDICMDARG); cmdcon = readl(host->base + S3C2410_SDICMDCON); cmdsta = readl(host->base + S3C2410_SDICMDSTAT); r0 = readl(host->base + S3C2410_SDIRSP0); r1 = readl(host->base + S3C2410_SDIRSP1); r2 = readl(host->base + S3C2410_SDIRSP2); r3 = readl(host->base + S3C2410_SDIRSP3); timer = readl(host->base + S3C2410_SDITIMER); bsize = readl(host->base + S3C2410_SDIBSIZE); datcon = readl(host->base + S3C2410_SDIDCON); datcnt = readl(host->base + S3C2410_SDIDCNT); datsta = readl(host->base + S3C2410_SDIDSTA); fsta = readl(host->base + S3C2410_SDIFSTA); imask = readl(host->base + host->sdiimsk); dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n", prefix, con, pre, timer); dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n", prefix, cmdcon, cmdarg, cmdsta); dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]" " DSTA:[%08x] DCNT:[%08x]\n", prefix, datcon, fsta, datsta, datcnt); dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]" " R2:[%08x] R3:[%08x]\n", prefix, r0, r1, r2, r3); } static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, int stop) { snprintf(host->dbgmsg_cmd, 300, "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u", host->ccnt, (stop ? " (STOP)" : ""), cmd->opcode, cmd->arg, cmd->flags, cmd->retries); if (cmd->data) { snprintf(host->dbgmsg_dat, 300, "#%u bsize:%u blocks:%u bytes:%u", host->dcnt, cmd->data->blksz, cmd->data->blocks, cmd->data->blocks * cmd->data->blksz); } else { host->dbgmsg_dat[0] = '\0'; } } static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd, int fail) { unsigned int dbglvl = fail ? dbg_fail : dbg_debug; if (!cmd) return; if (cmd->error == 0) { dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n", host->dbgmsg_cmd, cmd->resp[0]); } else { dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n", cmd->error, host->dbgmsg_cmd, host->status); } if (!cmd->data) return; if (cmd->data->error == 0) { dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat); } else { dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n", cmd->data->error, host->dbgmsg_dat, readl(host->base + S3C2410_SDIDCNT)); } } #else static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd, int fail) { } static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, int stop) { } static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { } #endif /* CONFIG_MMC_DEBUG */ /** * s3cmci_host_usedma - return whether the host is using dma or pio * @host: The host state * * Return true if the host is using DMA to transfer data, else false * to use PIO mode. Will return static data depending on the driver * configuration. */ static inline bool s3cmci_host_usedma(struct s3cmci_host *host) { #ifdef CONFIG_MMC_S3C_PIO return false; #elif defined(CONFIG_MMC_S3C_DMA) return true; #else return host->dodma; #endif } /** * s3cmci_host_canpio - return true if host has pio code available * * Return true if the driver has been compiled with the PIO support code * available. */ static inline bool s3cmci_host_canpio(void) { #ifdef CONFIG_MMC_S3C_PIO return true; #else return false; #endif } static inline u32 enable_imask(struct s3cmci_host *host, u32 imask) { u32 newmask; newmask = readl(host->base + host->sdiimsk); newmask |= imask; writel(newmask, host->base + host->sdiimsk); return newmask; } static inline u32 disable_imask(struct s3cmci_host *host, u32 imask) { u32 newmask; newmask = readl(host->base + host->sdiimsk); newmask &= ~imask; writel(newmask, host->base + host->sdiimsk); return newmask; } static inline void clear_imask(struct s3cmci_host *host) { u32 mask = readl(host->base + host->sdiimsk); /* preserve the SDIO IRQ mask state */ mask &= S3C2410_SDIIMSK_SDIOIRQ; writel(mask, host->base + host->sdiimsk); } /** * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled * @host: The host to check. * * Test to see if the SDIO interrupt is being signalled in case the * controller has failed to re-detect a card interrupt. Read GPE8 and * see if it is low and if so, signal a SDIO interrupt. * * This is currently called if a request is finished (we assume that the * bus is