STBx25xx Digital Set-Top Box Integrated
Controllers
Datasheet
Dec. 12, 2002- IBM Confidential
STBx25xx Digital Set-Top Box Integrated Controllers
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Copyright and Disclaimer
Copyright International Business Machines Corporation 2001, 2002
All Rights Reserved
Printed in the United States of America 12-2002
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or
both.
IBM IBM Logo
CoreConnect PowerPC
PowerPC 405
Dolby is registered trademark of Dolby Laboratories.
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document
are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction
could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not
affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or
implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this
document was obtained in specific environments, and is presented as an illustration. The results obtained in other oper-
ating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be
liable for damages arising directly or indirectly from any use of the information contained in this document.
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The IBM home page can be found at
http://www.ibm.com
The IBM Microelectronics Division home page can be found at
http://www.chips.ibm.com
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Table of Contents
Copyright and Disclaimer .................................................................................................................... 2
List of Tables ................................................................................................................ 23
List of Figures .............................................................................................................. 27
1. Product Overview ..................................................................................................... 31
1.1 Features ......................................................................................................................................... 31
1.2 Description .................................................................................................................................... 31
1.3 Ordering Information .................................................................................................................... 32
1.4 Conventions and Notation ........................................................................................................... 32
1.5 Licensing Requirements .............................................................................................................. 33
1.5.1 Dolby Digital Licensing .......................................................................................................... 33
1.5.2 Macrovision Licensing ........................................................................................................... 33
1.5.3 NDS ICAM Licensing ............................................................................................................. 34
1.5.4 DTS and DTS Digital Out Licensing ...................................................................................... 34
1.6 Architecture and Subsystem Information ................................................................................... 35
1.6.1 PowerPC 405D4 Processor Subsystem ................................................................................ 35
1.6.1.1 PowerPC 405 CPU ......................................................................................................... 36
1.6.1.2 Universal Interrupt Controller ......................................................................................... 36
1.6.1.3 Clock and Power Management ...................................................................................... 36
1.6.2 Memory Interface Subsystem ................................................................................................ 36
1.6.2.1 Direct Memory Access Controller ................................................................................... 36
1.6.2.2 External Bus Interface Unit ............................................................................................. 37
1.6.2.3 SDRAM Controllers ........................................................................................................ 37
1.6.2.4 Processor Local Bus ...................................................................................................... 37
1.6.3 Digital Audio/Video Subsystem ............................................................................................. 37
1.6.3.1 MPEG-2 Transport Demultiplexer .................................................................................. 38
1.6.3.2 MPEG-2 Video Decoder ................................................................................................. 38
1.6.3.3 MPEG-2/Dolby Digital Audio Decoder ............................................................................ 39
1.6.3.4 NTSC/PAL/SECAM Digital Encoder Unit with Macrovision Copy Protection ................. 40
1.6.4 Peripheral Subsystem ........................................................................................................... 41
1.6.4.1 General Purpose Timer .................................................................................................. 41
1.6.4.2 Pulse Width Modulation .................................................................................................. 41
1.6.4.3 Inter-Integrated Circuit (I
2
C) Units .................................................................................. 41
1.6.4.4 Smart Card Interface Units ............................................................................................. 41
1.6.4.5 UART 750 Serial Communication Controllers ................................................................ 42
1.6.4.6 Synchronous Serial Port ................................................................................................. 42
1.6.4.7 Serial Controller Port ...................................................................................................... 42
1.6.4.8 General Purpose I/O Controller ...................................................................................... 42
1.6.4.9 IR Receiver ..................................................................................................................... 42
1.6.4.10 Real Time Clock / Front Panel Controller ..................................................................... 43
1.7 Signal and I/O Information ........................................................................................................... 43
1.7.1 Signals Sorted by Signal Name ............................................................................................. 43
1.7.2 I/O Signal Descriptions .......................................................................................................... 52
1.8 I/O Timing Diagrams ..................................................................................................................... 59
1.8.1 AC Specifications .................................................................................................................. 59
1.9 Electrical Information ................................................................................................................... 68
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1.9.1 Drivers/Receivers ................................................................................................................... 68
1.9.2 DC Electrical Characteristics ................................................................................................. 69
1.9.2.1 Operating Conditions ...................................................................................................... 69
1.9.2.2 Recommended Connections .......................................................................................... 70
1.9.2.3 Absolute Maximum Ratings ............................................................................................ 72
1.9.2.4 Power Considerations .................................................................................................... 72
1.10 Mechanical Information .............................................................................................................. 73
1.11 Development Support ................................................................................................................. 74
1.11.1 Debug .................................................................................................................................. 74
1.11.2 Tools and Enablement ......................................................................................................... 74
1.11.3 Technical Library .................................................................................................................. 74
2. Configuration and Initialization ............................................................................... 75
2.1 STBx25xx Initialization ................................................................................................................. 75
2.1.1 Initialization Sequence ........................................................................................................... 75
2.1.2 Configuration Signals ............................................................................................................. 75
2.2 I/O Configuration ........................................................................................................................... 76
2.3 CIC and GPIO Registers Description ........................................................................................... 77
2.3.1 CIC Registers Description ...................................................................................................... 77
2.3.1.1 CIC Control Register (CICCR) ........................................................................................ 78
2.3.1.2 CIC Video Control Register (CICVCR) ........................................................................... 80
2.3.1.3 CIC BOOT Register (CICBOOT) .................................................................................... 81
2.3.1.4 CIC Select3 Register (CICSEL3) .................................................................................... 82
2.3.2 General Purpose I/O (GPIO) .................................................................................................. 83
2.3.3 General Purpose I/O (GPIO) Registers Description .............................................................. 85
2.3.3.1 GPIO Output Operation .................................................................................................. 85
2.3.3.2 GPIO Output Enable Control .......................................................................................... 86
2.3.3.3 GPIO Input Operation ..................................................................................................... 86
2.3.3.4 GPIO Output Register (GPO) ......................................................................................... 88
2.3.3.5 GPIO Three-State Control Register (GPTC) .................................................................. 89
2.3.3.6 GPIO Output Select Register (GPOS) ............................................................................ 90
2.3.3.7 GPIO Three-State Select Register (GPTS) .................................................................... 92
2.3.3.8 GPIO Open Drain Register (GPOD) ............................................................................... 94
2.3.3.9 GPIO Input Register (GPI) .............................................................................................. 95
2.3.3.10 GPIO Input Select Registers (GPIS1, GPIS2, GPIS3) ................................................. 96
2.3.3.11 GPIO Programming Example ....................................................................................... 98
2.4 Memory Configuration ................................................................................................................ 100
2.4.1 External Bus Interface Unit (EBIU) Controller ...................................................................... 101
2.4.1.1 EBIU Controller External Signals .................................................................................. 101
2.4.2 EBIU Operations .................................................................................................................. 103
2.4.2.1 Allocating Memory Regions .......................................................................................... 103
2.4.2.2 Aligning Memory Region Base Address to Match Region Size .................................... 103
2.4.2.3 Attaching Devices to the External Bus ......................................................................... 103
2.4.2.4 Bus Width after Reset ................................................................................................... 104
2.4.3 EBIU Controller Operations ................................................................................................. 104
2.4.3.1 Parameter Definitions ................................................................................................... 106
2.4.3.2 SRAM Read Example ................................................................................................... 107
2.4.3.3 SRAM Write Example ................................................................................................... 108
2.4.3.4 Device-Paced Transfers ............................................................................................... 109
2.4.3.5 SRAM Device-Paced Read Example ........................................................................... 111
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2.4.3.6 SRAM Device-Paced Write Example ........................................................................... 113
2.4.3.7 SRAM Burst Mode ........................................................................................................ 115
2.4.4 EBIU Registers Description ................................................................................................. 120
2.4.4.1 Cross-Bar Switch Configuration Register (CBSCR) ..................................................... 121
2.4.4.2 Bus Region Configuration Registers High (BRCRH0:BRCRH7) .................................. 122
2.4.4.3 Bus Region Configuration Registers (BRCR0:BRCR7) ............................................... 123
2.4.4.4 Bus Error Address Register (BEAR) ............................................................................ 127
2.4.4.5 Bus Error Status Register (BESR) ............................................................................... 128
2.4.4.6 Global EBIU Controls (BIUCR) ..................................................................................... 130
2.5 SDRAM Controllers ..................................................................................................................... 131
2.5.1 SDRAM Controller External Signals .................................................................................... 131
2.5.2 SDRAM Controller (SDRAMn) Operation ............................................................................ 131
2.5.2.1 SDRAM Performance and Pipelined Transfers ............................................................ 131
2.5.2.2 Error Handling .............................................................................................................. 132
2.5.2.3 SDRAMn Reset Functionality ....................................................................................... 132
2.5.2.4 SDRAMn Address Generation ..................................................................................... 133
2.5.2.5 Power-up, Initialization, and Reset ............................................................................... 133
2.5.2.6 Board Layout ................................................................................................................ 134
2.5.2.7 SDRAM Refresh ........................................................................................................... 134
2.5.3 SDRAM Control Registers Description ................................................................................ 135
2.5.3.1 Bus Error Status Register (SDRAM0BESR and SDRAM1BESR) ................................ 136
2.5.3.2 Bus Error Address Register (SDRAM0BEAR and SDRAM1BEAR) ............................. 137
2.5.3.3 Bank Registers (SDRAM0BR0:SDRAM0BR1 and SDRAM1BR0:SDRAM1BR1) ........ 138
2.5.3.4 Control Registers (SDRAM0CR0:SDRAM0CR1 and SDRAM1CR0:SDRAM1CR1) ... 139
2.6 Memory System Errors ............................................................................................................... 140
2.6.1 PLB-OPB Bridge Memory System Error Registers Description ........................................... 141
2.6.2 PLB Error Status Registers ................................................................................................. 142
2.6.2.1 PLB0 Error Status Register (PESR0) ........................................................................... 142
2.6.2.2 PLB1 Error Status Register (PESR1) ........................................................................... 144
2.6.3 PLB Error Address Registers (PEAR0 and PEAR1) ........................................................... 146
2.6.3.1 OPB Error Status Register (GESR) .............................................................................. 147
2.6.3.2 OPB Error Address Register (GEAR) ........................................................................... 149
2.6.4 Memory Error Reporting ...................................................................................................... 150
2.7 Clock and Power Management (CPM) ....................................................................................... 151
2.7.1 CPM Overview ..................................................................................................................... 151
2.7.2 CPM Force Register (CPMFR) ............................................................................................ 152
2.8 Reset Operations ........................................................................................................................ 154
2.8.1 Chip Reset ........................................................................................................................... 154
2.8.2 System Reset ...................................................................................................................... 154
3. MPEG-2 Transport Demultiplexer .......................................................................... 155
3.1 MPEG-2 Transport Overview ...................................................................................................... 155
3.1.1 Transport Synchronization ................................................................................................... 155
3.1.2 DES Decoding ..................................................................................................................... 155
3.1.3 PID Filtering ......................................................................................................................... 155
3.1.3.1 Parser and Sync Bypass Modes .................................................................................. 155
3.1.4 Clock Recovery ................................................................................................................... 156
3.1.5 Descrambling ....................................................................................................................... 156
3.1.6 Data Processing .................................................................................................................. 156
3.1.6.1 Table Section Filtering .................................................................................................. 156