USGMII-Specificationcisco资源-CSDN文库

mac

需积分: 20 184 浏览量 2022-11-12 10:39:15 上传评论收藏 1.45MB PDF 举报

资源推荐

资源详情

资源评论

Date printed: 5/11/2017 USGMII Functional Specification: EDCS-1155168

A printed copy of this document is considered uncontrolled. Refer to the online version for the controlled revision.

Document Number

EDCS-1155168

Based on

Template

EDCS-189229 Rev 20

Created By

Amrik Bains

USGMII Specification

The Universal Serial Gigabit Media Independent Interface (USGMII) is an extension of current

SGMII and QSGMII. USGMII provides flexibility to add new features while maintaining

backward compatibility. Previous definition/implementations cover single (SGMII) and quad

(QSGMII) options. This specification define USGMII option to support 4x1GE/8 x1GE network

ports and 5G/10G PHY/MAC SERDES speed respectively:

• Convey 4 to 8 ports of network data and port speed between a 10/100/1000

PHY and a MAC with significantly less signal pins than required for GMII &

SGMII.

• Utilize a 8B/10B PCS to maintain compatibility with SGMII/QSGMII

• USGMII interface operates as Full Duplex, while network interface supports

both half and full duplex modes.

• Ability to send Packet Channel Header to support programmable information

exchange between PH and MAC, for example PTP time stamp from PHY to

MAC to improve accuracy/jitter on encrypted PTP packet and MACSec is in the

ASIC

• Can be configured to support backward compatibility with SGMII and

QSGMII

Modification History

Revision

Date

Originator

Comments

3.0

11/12/2015

Amrik Bains

First general release

3.1

05/12/2016

Amrik Bains

Typo Fix

3.2

09/19/2016

Amrik Bains

Typo fix for Q-USGMII speed from 10G to 5G

3.3

11/02/2016

Amrik Bains

Typo correction for Extesnion Field Type to:

01: Extension Field contains Tag/Signature associated

with for time-stamp to be taken by the PHY

4.0

02/10/2017

Amrik Bains

Added Pre-emption Features – PCH changes

4.1

05/11/2017

Amrik Bains

With pre-emption, additional PTP enable is required on

egress – see table 5

Date printed: 5/11/2017 USGMII Functional Specification: EDCS-1155168

A printed copy of this document is considered uncontrolled. Refer to the online version for the controlled revision.

Table of Content

Modification History ....................................................................................................................... 1

1 Overview .................................................................................................................................. 5

1.1 Auto-neg Mechanism ...................................................................................................... 11

1.2 Packet Control Header ..................................................................................................... 12

2 Implementation Specification ................................................................................................ 15

2.1 Signal Mapping at the PHY side ..................................................................................... 16

2.2 Signal Mapping at the MAC Side.................................................................................... 19

2.2.1 Auto-neg Control Information Exchanged between Links ....................................... 20

2.2.2 Data Information Transferred Between Links .......................................................... 20

2.2.3 Scrambler/De-scrambler ........................................................................................... 21

2.2.4 Packet Control Header PHY/ASIC ........................................................................... 23

2.3 Electrical Specification .................................................................................................... 27

2.3.1 SGMII – 1.25 Gbps Electrical Specification ............................................................ 27

2.3.2 Q-USGMII – 5.0 Gbps Electrical Specification ....................................................... 27

2.3.3 O-USGMII – 10.0 Gbps Electrical Specification ..................................................... 34

Table of Figures

Figure1: Standard (IEEE 802.3 PCS/PMA) and Modified Transmit Path Diagram ...................... 6

Figure 2: Standard (IEEE 802.3 PCS/PMA) and Modified Transmit Path Diagrams .................... 7

Figure 3: Examples of Bit Positions across Different Interface Mode ........................................... 8

Figure 4: Packet Control Header (PCH) Format........................................................................... 12

Figure 5: USGMII Features/Connectivity .................................................................................... 15

Figure 6: Phy Functional Block (One Port) .................................................................................. 16

Figure 7: MAC Functional Block (One Port) ............................................................................... 19

Figure 8: Data sampling in 100 Mbit/s modes .............................................................................. 21

Figure 9: Scrambler/De-scrambler for 10G Mode ........................................................................ 22

Figure 10: Packet Control Header Mapping to Pre-amble with SOP and Checksum .................. 23

Figure 11: Bit order for Serial CRC Computation ........................................................................ 25

Figure 12: CRC Calculation.......................................................................................................... 26

Figure 13: Driver and Receiver Eye Mask ................................................................................... 32

Figure 14: Driver and Receiver Differential Return Loss ............................................................ 32

Figure 15: Definition of Driver Amplitude and Swing ................................................................. 33

Figure 16: Interconnect Loss Template for Q-USGMII Channel ................................................. 34

Date printed: 5/11/2017 USGMII Functional Specification: EDCS-1155168

A printed copy of this document is considered uncontrolled. Refer to the online version for the controlled revision.

Definitions

MII - Media Independent Interface: A digital interface that provides a 4-bit wide datapath between a 10/100 Mbit/s

PHY and a MAC sublayer. Since MII is a subset of GMII, in this document, we will use the term “GMII” to cover

all of the specification regarding the MII interface.

GMII- Gigabit Media Independent Interface: A digital interface that provides an 8-bit wide datapath between a

1000 Mbit/s PHY and a MAC sublayer. It also supports the 4-bit wide MII interface as defined in the IEEE 802.3z

specification. In this document, the term “GMII” covers all 10/100/1000 Mbit/s interface operations.

SGMII- Serial Gigabit Media Independent Interface: A digital interface that provides a 1.25 Gbps serial dual-data-

rate datapath between a 1000 Mbit/s PHY and a MAC sublayer. Refer to ENG-46158 or ftp://ftp-

eng.cisco.com/smii/smii.html for details.

QSGMII- Quad Serial Gigabit Media Independent Interface: A digital interface that provides a 5.0 Gbps serial

datapath between four 1000 Mbit/s PHY ports and a MAC sublayer. Refer to EDCS-540103 or ftp://ftp-

eng.cisco.com/smii/smii.html for details.

USGMII - Universal Serial Gigabit Media Independent Interface: A digital interface that provides capability to

carry multi-port/multi-rate serial datapath between PHY ports and a MAC sublayer using 8B/10B coding. Refer to

EDCS 1155168

USXGMII- Universal Serial 10 Gigabit Media Independent Interface: A digital interface that provides capability to

carry multiport/multi-rate serial datapath between PHY ports and a MAC sublayer using 64B/66B coding. Refer to

appropriate specification based on media type, network data rate and PHY/MAC SERDES speed.

LPI- Low Power Idle: An alternative form of idle signaling that is used by the MAC to indicate that the PHY may

enter a low power state and signal this change of state to the link partner; and is used by the PHY to signal to the

MAC that the link partner has entered a low power state. The functions are defined by IEEE 802.3az in IEEE 802.3

clauses 22, 24, 25 (for 100Mb/s); 35, 36, 40, 70 (for 1Gbps); 46, 48, 49, 55, 71, 72 (for 10Gbps); and 78 (for overall

descriptions).

Date printed: 5/11/2017 USGMII Functional Specification: EDCS-1155168

A printed copy of this document is considered uncontrolled. Refer to the online version for the controlled revision.

1 Overview

USGMII uses two data signals in each direction to convey frame data and link rate information

between a multi-port 10/100/1000 PHY and Ethernet MAC. From architecture perspective, the

data rate using CDR technology to recover the clock at the MAC and PHY interfaces can be any

rate depending on number of ports and maximum speed per port. The SERDES rate can be as

high as 10Gbps (8x1GE). Due to the high speed of operation, each of these signal pairs are

realized as differential pairs thus optimizing signal integrity while minimizing system noise. The

table 1, below show current and next generation interface in term of number of port, port speed

and SERDES data rate.

Number of Data

ports

Data

Speed

per port

Number

of Part

Maximum

SERDES

Speed

(Gbps)

Comment

1-port

10/100/1000M

(SGMII)

10/100/1

000M

1.25

One Port, no PCH

4-port

10/100/1000M

(QSGMII)

10/100/1

000M

5.0

Maximum of 4 ports, no PCH

4-port

10/100/1000M

(Q-USGMII)

10/100/

1000M

5.0Gbps

Maximum of 4 ports with PCH

8-port

10/100/1000M

(O-USGMII)

10/100/

1000M

10.0Gbps

Maximum of 8 ports with PCH

Table 1: Examples of Current and Next Generation Interface Options

The other SERDES rates could be supported based on technology capability and network port

data rate requirements

A simple round-robin scheme is used to interleave 8-bit words from each port and multiplex to

create data stream that is encoded using 8B/10B PCS.

For 10Gbps operation, an optional/configurable scrambler/de-scrambler is placed at after the

Encoder and before Decoder to reduce effect of repetitive patterns that may occur with 8B/10B

coding. Refer to section 2.2.3 for more details.

Figure 1, compares the IEEE 802.3 PCS reference diagram before and after the USGMII

modification.

剩余35页未读，继续阅读

评论收藏

内容反馈

liuyongchong

粉丝: 3
资源: 11

USGMII-Specification cisco

最新资源

USGMII-Specification cisco

OCPP-1.6-Specification充电桩协议

OV9281-Preliminary-Specification-CSP5_Version-1-1_Omnivision.pdf

mipi-M-PHY-specification-v4-1-JEDEC-LIAISON-DISCLOSURE

Matter-1.0-Core-Specification.pdf

HAP-Specification-Non-Commercial-Version.zip

zigbee3.0 docs-13-0402-13-00zi-Base-Device-Behavior-Specification-2.pdf

07-5123-06-zigbee-cluster-library-specification (20).pdf

NVM-Express-Base-Specification-2_0-2021.06.02-Ratified-5.pdf

OpenRTB-Native-Ads-Specification-Final-1.2.pdf

zigbee-cluster-library-specification 2012版和最新版

ONVIF-CORE-SPECIFICATION

ASAM_XCP_Part2-Protocol-Layer-Specification_V1-1-0Cracked.pdf

1139-Ed.3-The-Technical-Specification-of-VDES_June-2019.pdf

lorawan-specification_v1.0.2_zh_cn_190102中文版.pdf

OpenRTB-API-Specification-Version-2-4-FINAL

OpenRTB-API-Specification-Version-2-5-FINAL.pdf

ONVIF-Core-Specification-v240

USB-Type-C-Specification-Release-1.3

ZigBee PRO 2015 全中文标准 docs-05-3474-21-0csg-zigbee-specification-CN.pdf

解决Win 10与不兼容VirtualBox操作过程文档+（附带软件）.zip

计算机网络知识点总结(谢希仁第八版).pdf

Xshell软件(配色方案&amp;高亮关键字/突出显示集)的相关文件

湖南科技大学《计算机网络》配套课件（PDF版）

《计算机网络自顶向下方法第7版》中文PDF+复习题问题中文版答案

计算机网络自顶向下方法第八版答案

H3C-iNode-PC-7.3-E0630

hevc视频扩展免费2.0.53348.0x64

quickping下载

matlab输入到abaqus

最新资源

Xshell软件(配色方案&高亮关键字/突出显示集)的相关文件