DP83640数据手册资源-CSDN文库

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### DP83640数据手册关键知识点解析 #### 一、概述 DP83640是一款由国家半导体公司推出的高精度物理层收发器（PHYTER），它支持IEEE 1588精确时间协议（Precision Time Protocol，PTP）。这款设备能够提供实时工业连接所需的最高水平的时钟同步精度。DP83640具有确定性低延迟的特点，并且不需要硬件定制即可与多种微控制器配合使用。其内置的IEEE 1588功能使得系统设计者可以在接近网络边缘的位置实现高精度的时间戳记录。 #### 二、主要特性 **IEEE 1588 V1 和 V2 支持** - DP83640支持IEEE 1588的第一版和第二版标准，确保了广泛的兼容性和灵活性。 **多种协议包支持** - 支持UDP/IPv4、UDP/IPv6以及第二层以太网包，这意味着它可以处理不同网络环境下的数据传输需求。 **IEEE 1588 时钟同步** - 提供基于IEEE 1588标准的时钟同步功能，这对于需要高度同步的应用场景至关重要。 **时间戳分辨率** - 提供高达8纳秒的时间戳分辨率，这对于需要极高精度时间同步的应用非常关键。 **亚100纳秒级别的主参考同步** - 允许将时钟与主参考源同步至低于100纳秒的级别，这是该设备的一个重要优势。 **GPIO触发和捕获** - 设备包含12个IEEE 1588 GPIO端口，用于触发或捕获事件，这为高级应用提供了更多的灵活性。 **确定性和低延迟** - 该设备提供确定性的低延迟性能，这对于实时通信非常重要。 **频率同步时钟输出** - 用户可以选择频率同步的时钟输出，以满足特定应用的需求。 **动态链路质量监控** - DP83640提供了动态链路质量监控功能，能够在标准操作期间实时监测链路质量，预测潜在故障。 **电缆诊断和长度检测** - 基于时域反射计（Time Domain Reflectometry，TDR）技术进行电缆诊断和长度检测。 **内置自测试** - 支持10/100Mbps的数据包内置自测试（BIST），有助于确保系统的可靠运行。 **无错误操作** - 在长达150米的CAT5电缆上实现无错误操作。 **ESD保护** - 提供8千伏的人体模型静电放电保护，增强了设备的耐用性和可靠性。 **I/O 和 MAC 接口** - 使用3.3伏的输入输出和媒体访问控制（MAC）接口。 **自动交叉线检测** - 支持10/100Mbps的自动交叉线检测（Auto-MDIX）。 **MAC 接口** - 支持修订版1.2的简化媒体独立接口（RMII）和媒体独立接口（MII）。 **串行管理接口** - 包含25兆赫兹的介质依赖接口时钟（MDC）和介质依赖接口（MDIO）串行管理接口。 **光纤接口** - 支持IEEE 802.3u标准的100BASE-FX光纤接口。 **JTAG 接口** - 遵循IEEE 1149.1标准的JTAG接口。 **可编程LED支持** - 可编程LED支持显示连接状态、10/100Mbps模式、双工模式、活动状态以及冲突检测。 **快速链路丢失检测** - 可选的100BASE-TX快速链路丢失检测功能。 **封装形式** - 采用48引脚LQFP封装，尺寸为7mm x 7mm。 #### 三、应用领域 DP83640因其出色的特性和灵活性，在多个领域都有广泛的应用： **工厂自动化** - **Ethernet/IP**：适用于工业以太网协议。 - **CIP Sync**：支持通用工业协议中的同步功能。 **测试与测量** - **LXI Standard**：符合远程测试和测量的LAN扩展标准。 **电信** - **基站**：适用于无线通信基站的同步需求。 **实时网络** - 支持需要高度同步的实时网络应用场景。通过上述解析可以看出，DP83640是一款高度集成、功能强大的以太网物理层收发器，不仅支持IEEE 1588精确时间协议，还提供了丰富的功能特性，适用于各种工业和通信领域的实时应用。

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February 26, 2008

DP83640

Precision PHYTER - IEEE® 1588 Precision Time Protocol

Transceiver

1.0 General Description

The DP83640 Precision PHYTER® device delivers the high-

est level of precision clock synchronization for real time in-

dustrial connectivity based on the IEEE 1588 standard. The

DP83640 has deterministic, low latency and allows choice of

microcontroller with no hardware customization required. The

integrated 1588 functionality allows system designers the

flexibility and precision of a close to the wire timestamp. The

three key 1588 features supported by the device are:

— Packet time stamps for clock synchronization

— Integrated IEEE 1588 synchronized clock generation

— Synchronized event triggering and time stamping through

GPIO

DP83640 offers innovative diagnostic features unique to Na-

tional Semiconductor, including dynamic monitoring of link

quality during standard operation for fault prediction. These

advanced features allow the system designer to implement a

fault prediction mechanism to detect and warn of deteriorating

and changing link conditions. This single port fast Ethernet

transceiver can support both copper and fiber media.

2.0 Applications

■

Factory Automation

—

Ethernet/IP

—

CIP Sync

■

Test and Measurement

—

LXI Standard

■

Telecom

—

Basestation

■

Real Time Networking

3.0 Features

■

IEEE 1588 V1 and V2 supported

■

UDP/IPv4, UDP/IPv6, and Layer2 Ethernet packets

supported

■

IEEE 1588 clock synchronization

■

Timestamp resolution of 8 ns

■

Allows sub 100 ns synchronization to master reference

■

12 IEEE 1588 GPIOs for trigger or capture

■

Deterministic, low transmit and receive latency

■

Selectable frequency synchronized clock output

■

Dynamic Link Quality monitoring

■

TDR based Cable Diagnostic and Cable Length Detection

■

10/100 Mb/s packet BIST (Built in Self Test)

■

Error-free Operation up to 150 meters CAT5 cable

■

ESD protection - 8 kV human body model

■

3.3 V I/Os and MAC interface

■

Auto-MDIX for 10/100 Mbps

■

RMII Rev. 1.2 and MII MAC interface

■

25 MHz MDC and MDIO Serial Management Interface

■

IEEE 802.3u 100BASE-FX Fiber Interface

■

IEEE 1149.1 JTAG

■

Programmable LED support for Link, 10 /100 Mb/s Mode,

Duplex, Activity, and Collision Detect

■

Optional 100BASE-TX fast link-loss detection

■

48 pin LQFP package (7mm) x (7mm)

4.0 System Diagram

30011217

PHYTER

is a registered trademark of National Semiconductor.

DP83640 Precision PHYTER - IEEE 1588 Precision Time Protocol Transceiver

Table of Contents
0 General Description ......................................................................................................................... 1
0 Applications .................................................................................................................................... 1
0 Features ........................................................................................................................................ 1
0 System Diagram .............................................................................................................................. 1
0 Block Diagram ................................................................................................................................ 6
0 Key IEEE 1588 Features .................................................................................................................. 6
1 IEEE 1588 SYNCHRONIZED CLOCK .............................................................................................. 7
1.1 IEEE 1588 Clock Output ............................................................................................................ 7
1.2 IEEE 1588 Clock Input .............................................................................................................. 8
2 PACKET TIMESTAMPS  ................................................................................................................ 8
2.1 IEEE 1588 Transmit Packet Parser and Timestamp ....................................................................... 8
2.1.1 One-Step Operation ............................................................................................................. 8
2.2 IEEE 1588 Receive Packet Parser and Timestamp ....................................................................... 8
2.2.1 Receive Timestamp Insertion ................................................................................................. 8
2.3 NTP Packet Timestamp ............................................................................................................. 8
3 EVENT TRIGGERING AND TIMESTAMPING ................................................................................... 8
3.1 IEEE 1588 Event Triggering ....................................................................................................... 8
3.2 IEEE 1588 Event Timestamping ................................................................................................. 8
4 PTP INTERRUPTS ........................................................................................................................ 8
5 GPIO ........................................................................................................................................... 8
0 Pin Layout ...................................................................................................................................... 9
0 Pin Descriptions ............................................................................................................................ 10
1 SERIAL MANAGEMENT INTERFACE ........................................................................................... 10
2 MAC DATA INTERFACE ..............................................................................................................  10
3 CLOCK INTERFACE ................................................................................................................... 12
4 LED INTERFACE ........................................................................................................................ 13
5 IEEE 1588 EVENT/TRIGGER/CLOCK INTERFACE ......................................................................... 13
6 JTAG INTERFACE ......................................................................................................................  13
7 RESET AND POWER DOWN ....................................................................................................... 14
8 STRAP OPTIONS .......................................................................................................................  15
9 10 Mb/s AND 100 Mb/s PMD INTERFACE ...................................................................................... 16
10 POWER SUPPLY PINS ..............................................................................................................  17
11 PACKAGE PIN ASSIGNMENTS .................................................................................................. 17
0 Configuration ................................................................................................................................ 18
1 MEDIA CONFIGURATION ............................................................................................................ 18
2 AUTO-NEGOTIATION .................................................................................................................  18
2.1 Auto-Negotiation Pin Control .................................................................................................... 18
2.2 Auto-Negotiation Register Control .............................................................................................  18
2.3 Auto-Negotiation Parallel Detection ........................................................................................... 19
2.4 Auto-Negotiation Restart .......................................................................................................... 19
2.5 Enabling Auto-Negotiation via Software .....................................................................................  19
2.6 Auto-Negotiation Complete Time .............................................................................................. 19
3 AUTO-MDIX ...............................................................................................................................  19
4 PHY ADDRESS .......................................................................................................................... 19
4.1 MII Isolate Mode .....................................................................................................................  19
4.2 Broadcast Mode .....................................................................................................................  20
5 LED INTERFACE ........................................................................................................................ 20
5.1 LEDs ..................................................................................................................................... 21
5.2 LED Direct Control ..................................................................................................................  21
6 HALF DUPLEX vs. FULL DUPLEX ................................................................................................  21
7 INTERNAL LOOPBACK ...............................................................................................................  21
8 POWER DOWN/INTERRUPT ....................................................................................................... 21
8.1 Power Down Control Mode ......................................................................................................  21
8.2 Interrupt Mechanisms .............................................................................................................. 22
9 ENERGY DETECT MODE ............................................................................................................ 22
10 LINK DIAGNOSTIC CAPABILITIES ............................................................................................. 22
10.1 Linked Cable Status .............................................................................................................. 22
10.1.1 Polarity Reversal .............................................................................................................. 22
10.1.2 Cable Swap Indication ...................................................................................................... 22
10.1.3 100 Mb Cable Length Estimation ........................................................................................  22
10.1.4 Frequency Offset Relative to Link Partner ............................................................................  22
10.1.5 Cable Signal Quality Estimation ..........................................................................................  22
10.2 Link Quality Monitor ...............................................................................................................  22
10.2.1 Link Quality Monitor Control and Status ...............................................................................  23
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DP83640

10.2.2 Checking Current Parameter Values ................................................................................... 23
10.2.3 Threshold Control .............................................................................................................  23
10.3 TDR Cable Diagnostics .......................................................................................................... 23
10.4 TDR Pulse Generator ............................................................................................................ 23
10.5 TDR Pulse Monitor ................................................................................................................ 24
10.6 TDR Control Interface ............................................................................................................  24
10.7 TDR Results .........................................................................................................................  24
11 BIST ........................................................................................................................................ 24
0 MAC Interface .............................................................................................................................  24
1 MII INTERFACE ........................................................................................................................ 24
1.1 Nibble-wide MII Data Interface ................................................................................................  25
1.2 Collision Detect ..................................................................................................................... 25
1.3 Carrier Sense .......................................................................................................................  25
2 REDUCED MII INTERFACE .......................................................................................................  25
2.1 RMII Master Mode ................................................................................................................. 26
2.2 RMII Slave Mode ..................................................................................................................  26
3 SINGLE CLOCK MII MODE ........................................................................................................  26
4 IEEE 802.3u MII SERIAL MANAGEMENT INTERFACE .................................................................. 26
4.1 Serial Management Register Access ....................................................................................... 26
4.2 Serial Management Access Protocol ........................................................................................  26
4.3 Serial Management Preamble Suppression ..............................................................................  27
5 PHY CONTROL FRAMES ..........................................................................................................  27
6 PHY STATUS FRAMES .............................................................................................................  28
0 Architecture ................................................................................................................................  28
1 100BASE-TX TRANSMITTER .....................................................................................................  28
1.1 Code-Group Encoding and Injection ........................................................................................  30
1.2 Scrambler ............................................................................................................................ 30
1.3 NRZ to NRZI Encoder ............................................................................................................  31
1.4 Binary to MLT-3 Convertor .....................................................................................................  31
2 100BASE-TX RECEIVER ........................................................................................................... 31
2.1 Analog Front End ..................................................................................................................  31
2.2 Digital Signal Processor ......................................................................................................... 31
2.2.1 Base Line Wander Compensation .......................................................................................  32
2.2.2 Digital Adaptive Equalization and Gain Control ..................................................................... 32
2.3 Signal Detect ........................................................................................................................ 32
2.4 MLT-3 to Binary Decoder ....................................................................................................... 32
2.5 Clock Recovery Module .........................................................................................................  33
2.6 NRZI to NRZ Decoder ........................................................................................................... 33
2.7 Serial to Parallel ...................................................................................................................  33
2.8 Descrambler .........................................................................................................................  33
2.9 Code-Group Alignment ..........................................................................................................  33
2.10 4B/5B Decoder ................................................................................................................... 33
2.11 100BASE-TX Link Integrity Monitor ........................................................................................  33
2.12 Bad SSD Detection .............................................................................................................. 33
3 100BASE-FX OPERATION ......................................................................................................... 33
3.1 100BASE-FX Transmit ........................................................................................................... 33
3.2 100BASE-FX Receive ........................................................................................................... 33
3.3 Far-End Fault .......................................................................................................................  33
4 10BASE-T TRANSCEIVER MODULE ..........................................................................................  34
4.1 Operational Modes ................................................................................................................ 34
4.2 Smart Squelch ......................................................................................................................  34
4.3 Collision Detection and SQE ................................................................................................... 34
4.4 Carrier Sense .......................................................................................................................  35
4.5 Normal Link Pulse Detection/Generation ..................................................................................  35
4.6 Jabber Function .................................................................................................................... 35
4.7 Automatic Link Polarity Detection and Correction ....................................................................... 35
4.8 Transmit and Receive Filtering ................................................................................................ 35
4.9 Transmitter ........................................................................................................................... 35
4.10 Receiver ............................................................................................................................  35
0 Reset Operation .......................................................................................................................... 35
1 HARDWARE RESET .................................................................................................................  35
2 FULL SOFTWARE RESET ......................................................................................................... 35
3 SOFT RESET ...........................................................................................................................  35
4 PTP RESET ..............................................................................................................................  35
0 Design Guidelines .......................................................................................................................  36
1 TPI NETWORK CIRCUIT ............................................................................................................ 36
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DP83640

2 FIBER NETWORK CIRCUIT ....................................................................................................... 37
3 ESD PROTECTION ...................................................................................................................  37
4 CLOCK IN (X1) RECOMMENDATIONS ........................................................................................ 37
0 Register Block .............................................................................................................................  39
1 REGISTER DEFINITION ............................................................................................................  45
1.1 Basic Mode Control Register (BMCR) ......................................................................................  46
1.2 Basic Mode Status Register (BMSR) ....................................................................................... 48
1.3 PHY Identifier Register #1 (PHYIDR1) .....................................................................................  49
1.4 PHY Identifier Register #2 (PHYIDR2) .....................................................................................  49
1.5 Auto-Negotiation Advertisement Register (ANAR) .....................................................................  50
1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) ........................................ 51
1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) ..........................................  52
1.8 Auto-Negotiate Expansion Register (ANER) .............................................................................  52
1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) ..........................................................  53
1.10 PHY Status Register (PHYSTS) ............................................................................................  54
1.11 MII Interrupt Control Register (MICR) ..................................................................................... 56
1.12 MII Interrupt Status and Event Control Register (MISR) ............................................................  57
1.13 Page Select Register (PAGESEL) .........................................................................................  59
2 EXTENDED REGISTERS - PAGE 0 .............................................................................................  59
2.1 False Carrier Sense Counter Register (FCSCR) ........................................................................  59
2.2 Receiver Error Counter Register (RECR) .................................................................................  59
2.3 100 Mb/s PCS Configuration and Status Register (PCSR) .......................................................... 60
2.4 RMII and Bypass Register (RBR) ............................................................................................  61
2.5 LED Direct Control Register (LEDCR) ...................................................................................... 62
2.6 PHY Control Register (PHYCR) ..............................................................................................  63
2.7 10Base-T Status/Control Register (10BTSCR) ..........................................................................  65
2.8 CD Test and BIST Extensions Register (CDCTRL1) ..................................................................  66
2.9 PHY Control Register 2 (PHYCR2) .......................................................................................... 67
2.10 Energy Detect Control (EDCR) ..............................................................................................  68
2.11 PHY Control Frames Configuration Register (PCFCR) ............................................................. 69
3 TEST REGISTERS - PAGE 1 ...................................................................................................... 70
3.1 Signal Detect Configuration (SD_CNFG), Page 1 ......................................................................  70
4 LINK DIAGNOSTICS REGISTERS - PAGE 2 ................................................................................ 71
4.1 100 Mb Length Detect Register (LEN100_DET), Page 2 ............................................................. 71
4.2 100 Mb Frequency Offset Indication Register (FREQ100), Page 2 ...............................................  71
4.3 TDR Control Register (TDR_CTRL), Page 2 .............................................................................  72
4.4 TDR Window Register (TDR_WIN), Page 2 .............................................................................. 73
4.5 TDR Peak Register (TDR_PEAK), Page 2 ................................................................................ 73
4.6 TDR Threshold Register (TDR_THR), Page 2 ...........................................................................  73
4.7 Variance Control Register (VAR_CTRL), Page 2 ....................................................................... 74
4.8 Variance Data Register (VAR_DATA), Page 2 .......................................................................... 74
4.9 Link Quality Monitor Register (LQMR), Page 2 ..........................................................................  75
4.10 Link Quality Data Register (LQDR), Page 2 ............................................................................. 77
4.11 Link Quality Monitor Register 2 (LQMR2), Page 2 ....................................................................  78
5 PTP 1588 BASE REGISTERS - PAGE 4 ...................................................................................... 79
5.1 PTP Control Register (PTP_CTL), Page 4 ................................................................................  79
5.2 PTP Time Data Register (PTP_TDR), Page 4 ........................................................................... 81
5.3 PTP Status Register (PTP_STS), Page 4 ................................................................................. 81
5.4 PTP Trigger Status Register (PTP_TSTS), Page 4 ....................................................................  82
5.5 PTP Rate Low Register (PTP_RATEL), Page 4 ......................................................................... 83
5.6 PTP Rate High Register (PTP_RATEH), Page 4 ....................................................................... 84
5.7 PTP Read Checksum (PTP_RDCKSUM), Page 4 .....................................................................  84
5.8 PTP Write Checksum (PTP_WRCKSUM), Page 4 ..................................................................... 84
5.9 PTP Transmit Timestamp Register (PTP_TXTS), Page 4 ........................................................... 85
5.10 PTP Receive Timestamp Register (PTP_RXTS), Page 4 .......................................................... 85
5.11 PTP Event Status Register (PTP_ESTS), Page 4 ....................................................................  86
5.12 PTP Event Data Register (PTP_EDATA), Page 4 ....................................................................  87
6 PTP 1588 CONFIGURATION REGISTERS - PAGE 5 ....................................................................  89
6.1 PTP Trigger Configuration Register (PTP_TRIG), Page 5 ........................................................... 89
6.2 PTP Event Configuration Register (PTP_EVNT), Page 5 ............................................................  90
6.3 PTP Transmit Configuration Register 0 (PTP_TXCFG0), Page 5 .................................................  91
6.4 PTP Transmit Configuration Register 1 (PTP_TXCFG1), Page 5 .................................................  92
6.5 PHY Status Frame Configuration Register 0 (PSF_CFG0), Page 5 ..............................................  92
6.6 PTP Receive Configuration Register 0 (PTP_RXCFG0), Page 5, .................................................  93
6.7 PTP Receive Configuration Register 1 (PTP_RXCFG1), Page 5 .................................................. 94
6.8 PTP Receive Configuration Register 2 (PTP_RXCFG2), Page 5 .................................................. 94
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DP83640

6.9 PTP Receive Configuration Register 3 (PTP_RXCFG3), Page 5 .................................................. 95
6.10 PTP Receive Configuration Register 4 (PTP_RXCFG4), Page 5 ................................................  96
6.11 PTP Temporary Rate Duration Low Register (PTP_TRDL), Page 5 ............................................ 96
6.12 PTP Temporary Rate Duration High Register (PTP_TRDH), Page 5 ...........................................  97
7 PTP 1588 CONFIGURATION REGISTERS - PAGE 6 ....................................................................  97
7.1 PTP Clock Output Control Register (PTP_COC), Page 6 ............................................................ 97
7.2 PHY Status Frame Configuration Register 1 (PSF_CFG1), Page 6 ..............................................  98
7.3 PHY Status Frame Configuration Register 2 (PSF_CFG2), Page 6 ..............................................  98
7.4 PHY Status Frame Configuration Register 3 (PSF_CFG3), Page 6 ..............................................  98
7.5 PHY Status Frame Configuration Register 4 (PSF_CFG4), Page 6 ..............................................  98
7.6 PTP SFD Configuration Register (PTP_SFDCFG), Page 6 .........................................................  99
7.7 PTP Interrupt Control Register (PTP_INTCTL), Page 6 ..............................................................  99
7.8 PTP Clock Source Register (PTP_CLKSRC), Page 6 .................................................................  99
7.9 PTP Ethernet Type Register (PTP_ETR), Page 6 ......................................................................  99
7.10 PTP Offset Register (PTP_OFF), Page 6 ..............................................................................  100
7.11 PTP GPIO Monitor Register (PTP_GPIOMON), Page 6 ..........................................................  100
7.12 PTP Receive Hash Register (PTP_RXHASH), Page 6 ............................................................  100
0 Absolute Maximum Ratings .........................................................................................................  101
0 AC and DC Specifications ...........................................................................................................  101
1 DC SPECIFICATIONS .............................................................................................................  101
2 AC SPECIFICATIONS ..............................................................................................................  102
2.1 Power Up Timing ................................................................................................................  102
2.2 Reset Timing ......................................................................................................................  103
2.3 MII Serial Management Timing .............................................................................................  104
2.4 100 Mb/s MII Transmit Timing ...............................................................................................  104
2.5 100 Mb/s MII Receive Timing ................................................................................................  105
2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing .........................................  105
2.7 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion Timing ...................................  106
2.8 100BASE-TX Transmit Timing (t
R/F
 & Jitter) ............................................................................  106
2.9 100BASE-TX and 100BASE-FX MII Receive Packet Latency Timing .........................................  107
2.10 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion Timing  .................................  107
2.11 10 Mb/s MII Transmit Timing ...............................................................................................  108
2.12 10 Mb/s MII Receive Timing ................................................................................................  108
2.13 10BASE-T MII Transmit Timing (Start of Packet) ...................................................................  109
2.14 10BASE-T MII Transmit Timing (End of Packet) ....................................................................  109
2.15 10BASE-T MII Receive Timing (Start of Packet) ....................................................................  110
2.16 10BASE-T MII Receive Timing (End of Packet) .....................................................................  110
2.17 10 Mb/s Heartbeat Timing  ..................................................................................................  111
2.18 10 Mb/s Jabber Timing  ......................................................................................................  111
2.19 10BASE-T Normal Link Pulse Timing ...................................................................................  112
2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing ......................................................................  112
2.21 100BASE-TX Signal Detect Timing  .....................................................................................  113
2.22 100 Mb/s Internal Loopback Timing  .....................................................................................  113
2.23 10 Mb/s Internal Loopback Timing  ......................................................................................  114
2.24 RMII Transmit Timing (Slave Mode) .....................................................................................  114
2.25 RMII Transmit Timing (Master Mode) ...................................................................................  115
2.26 RMII Receive Timing (Slave Mode) ......................................................................................  116
2.27 RMII Receive Timing (Master Mode) ....................................................................................  117
2.28 RX_CLK Timing (RMII Master Mode) ...................................................................................  118
2.29 CLK_OUT Timing (RMII Slave Mode) ...................................................................................  118
2.30 Single Clock MII (SCMII) Transmit Timing  ............................................................................  119
2.31 Single Clock MII (SCMII) Receive Timing ..............................................................................  120
2.32 100 Mb/s X1 to TX_CLK Timing ..........................................................................................  121
0 Physical Dimensions ..................................................................................................................  122
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DP83640