################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA+彩条显示+ZYBO(这是一个特别完整的工程代码)
共234个文件
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v:22个
rst:19个
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本实验涉及到 FPGA 编程、彩条图像处理和 HDMI 输出等技术,是一个非常有挑战性和实用性的实验。在学习本实验前,需要学生具备一定的电子工程、计算机科学以及数字信号处理的基础知识,并熟悉 Verilog HDL 和 Xilinx Vivado 开发环境。 该实验对于电子工程、计算机科学等专业的高年级本科生或研究生而言,是一个非常好的学习和探索平台。首先,通过本实验可以深入了解 FPGA 的原理和实践技巧,了解如何使用 FPGA 进行数字信号处理和嵌入式系统开发。其次,在本实验中,学生需要学习如何使用彩条图像处理技术,将输入信号进行处理后输出到 HDMI 接口上。这种技术在视频监控、数字广告牌、视频游戏等领域中得到了广泛应用,具有很高的现实意义。 此外,通过完成本实验,学生们还可以了解到如何使用 Zybo 开发板进行 FPGA 实验。Zybo 开发板是一款功能强大的嵌入式开发板,配备了Xilinx Zynq-7000 SoC,集成了双核 ARM Cortex-A9 处理器和可编程逻辑部分,可以帮助学生们更好地理解和掌握 FPGA 和嵌入式系统开发的相关知识。
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FPGA+彩条显示+ZYBO(这是一个特别完整的工程代码) (234个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
hdmi_colorbar_top.bit 3.86MB
hdmi_colorbar_top_routed.dcp 317KB
hdmi_colorbar_top_placed.dcp 299KB
hdmi_colorbar_top_opt.dcp 259KB
hdmi_colorbar_top.dcp 45KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
compile.do 691B
compile.do 667B
compile.do 626B
compile.do 616B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 195B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 478B
run.f 462B
usage_statistics_webtalk.html 25KB
xsim.ini 25KB
vivado.jou 2KB
vivado_15132.backup.jou 972B
vivado_21296.backup.jou 732B
vivado.jou 732B
vivado.jou 726B
vivado.jou 724B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 43KB
runme.log 32KB
vivado.log 29KB
runme.log 23KB
vivado_15132.backup.log 2KB
hdmi_colorbar.lpr 343B
elab.opt 188B
vivado.pb 74KB
vivado.pb 37KB
place_design.pb 17KB
route_design.pb 15KB
opt_design.pb 11KB
write_bitstream.pb 6KB
init_design.pb 4KB
hdmi_colorbar_top_power_summary_routed.pb 728B
clk_wiz_0_utilization_synth.pb 224B
hdmi_colorbar_top_utilization_placed.pb 224B
hdmi_colorbar_top_utilization_synth.pb 224B
vivado.pb 149B
hdmi_colorbar_top_timing_summary_routed.pb 108B
hdmi_colorbar_top_methodology_drc_routed.pb 52B
hdmi_colorbar_top_route_status.pb 44B
hdmi_colorbar_top_drc_routed.pb 37B
hdmi_colorbar_top_drc_opted.pb 37B
hdmi_colorbar_top_bus_skew_routed.pb 30B
vlog.prj 251B
hdmi_colorbar_top_timing_summary_routed.rpt 212KB
hdmi_colorbar_top_io_placed.rpt 118KB
hdmi_colorbar_top_clock_utilization_routed.rpt 16KB
hdmi_colorbar_top_utilization_placed.rpt 9KB
hdmi_colorbar_top_power_routed.rpt 9KB
hdmi_colorbar_top_utilization_synth.rpt 7KB
clk_wiz_0_utilization_synth.rpt 6KB
hdmi_colorbar_top_control_sets_placed.rpt 4KB
hdmi_colorbar_top_methodology_drc_routed.rpt 2KB
hdmi_colorbar_top_drc_routed.rpt 2KB
hdmi_colorbar_top_drc_opted.rpt 2KB
hdmi_colorbar_top_bus_skew_routed.rpt 969B
hdmi_colorbar_top_route_status.rpt 588B
hdmi_colorbar_top_timing_summary_routed.rpx 180KB
hdmi_colorbar_top_power_routed.rpx 76KB
hdmi_colorbar_top_bus_skew_routed.rpx 1KB
hdmi_colorbar_top_methodology_drc_routed.rpx 841B
hdmi_colorbar_top_drc_routed.rpx 360B
hdmi_colorbar_top_drc_opted.rpx 359B
.vivado.begin.rst 446B
.vivado.begin.rst 224B
.vivado.begin.rst 223B
.route_design.begin.rst 185B
.opt_design.begin.rst 185B
.write_bitstream.begin.rst 185B
.place_design.begin.rst 185B
.init_design.begin.rst 185B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
.vivado.end.rst 0B
.init_design.end.rst 0B
共 234 条
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