################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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温馨提示
本实验主要涉及到FPGA编程、图像灰度化处理和Verilog HDL编程等技术,适合电子工程、计算机科学等专业的高年级本科生或研究生进行学习和探究。学生需要具备一定的数字电路设计和Verilog HDL编程基础知识,并熟悉Vivado开发环境和ZYBO开发板。 该实验的使用场景主要包括数字信号处理、嵌入式系统开发、视频图像处理等领域。通过本实验,学生们可以深入了解FPGA编程原理和应用技巧,掌握图像灰度化处理技术,以及如何在ZYBO开发板上进行实际操作。此外,在实验中,学生还将学习到如何使用Vivado开发环境进行FPGA设计和验证,以及如何进行调试和优化,从而更好地完成实验任务。 对于电子工程、计算机科学等专业的高年级本科生或研究生而言,参加本实验不仅可以提高他们的综合应用能力和创新思维水平,而且还能够帮助他们更好地理解数字电路设计和FPGA编程的相关知识,并加深对嵌入式系统开发的理解。此外,本实验也适合那些对数字信号处理、图像处理等领域感兴趣的人进行学习和探索。 在实验过程中,学生们需要面对一系列挑战性任务,如FPGA设计和调试、图像灰度化处理、Verilog HDL编程等。
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FPGA+图像灰度化显示+ZYBO+verilog(这是一个特别完整的工程代码) (428个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_running__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
simulate.bat 1KB
compile.bat 838B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
cat.bmp 198KB
xsim_2.c 152KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
img.coe 461KB
xsim.dbg 103KB
blk_mem_gen_img.dcp 729KB
blk_mem_gen_img.dcp 729KB
blk_mem_gen_img.dcp 727KB
blk_mem_gen_img.dcp 727KB
blk_mem_gen_img.dcp 727KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
compile.do 852B
compile.do 818B
compile.do 768B
compile.do 754B
compile.do 701B
compile.do 677B
compile.do 636B
compile.do 626B
simulate.do 346B
simulate.do 346B
simulate.do 345B
simulate.do 311B
simulate.do 306B
simulate.do 306B
elaborate.do 217B
simulate.do 207B
simulate.do 195B
elaborate.do 183B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
xsimk.exe 1.14MB
run.f 599B
run.f 579B
run.f 488B
run.f 472B
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
xsim.ini 26KB
xsim.ini 25KB
xsim.ini 25KB
xsimSettings.ini 1KB
vivado_6816.backup.jou 14KB
vivado_28280.backup.jou 9KB
vivado_27012.backup.jou 1KB
vivado_28376.backup.jou 1KB
vivado_24072.backup.jou 928B
webtalk.jou 885B
webtalk_21936.backup.jou 885B
webtalk_25152.backup.jou 860B
webtalk_16152.backup.jou 860B
vivado.jou 773B
vivado_21704.backup.jou 761B
vivado_23456.backup.jou 761B
vivado.jou 755B
vivado.jou 754B
vivado.jou 667B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
vivado_6816.backup.log 12.38MB
vivado_28280.backup.log 187KB
runme.log 44KB
runme.log 23KB
vivado_27012.backup.log 3KB
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