¸½ ¼
¸½Â¼1 ÇÀ´ð¼ø±ðÄ£¿éVHDL³ÌÐò£¨QDJB.VHD£©
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY QDJB IS
PORT (CLR: IN STD_LOGIC;
CLK: IN STD_LOGIC;
A, B, C, D: IN STD_LOGIC;
A1, B1, C1, D1: OUT STD_LOGIC;
G: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END QDJB;
ARCHITECTURE ART OF QDJB IS
CONSTANT W1: STD_LOGIC_VECTOR:="0001";
CONSTANT W2: STD_LOGIC_VECTOR:="0010";
CONSTANT W3: STD_LOGIC_VECTOR:="0100";
CONSTANT W4: STD_LOGIC_VECTOR:="1000";
BEGIN
PROCESS (CLR, A, B, C, D)
BEGIN
IF CLR='1' THEN G<="0000";
ELSIF (A='1'AND B='0'AND C='0'AND D='0') THEN
A1<='1'; B1<='0'; C1<='0'; D1<='0'; G<=W1;
ELSIF (A='0'AND B='1'AND C='0'AND D='0') THEN
A1<='0'; B1<='1'; C1<='0'; D1<='0'; G<=W2;
ELSIF (A='0'AND B='0'AND C='1'AND D='0') THEN
A1<='0'; B1 <='0'; C1<='1'; D1<='0'; G<=W3;
ELSIF (A='0'AND B='0'AND C='0'AND D='1') THEN
A1<='0'; B1 <='0'; C1<='0'; D1<='1'; G<=W4;
END IF;
END PROCESS;
END ART;
¸½Â¼2 ÇÀ´ð¼Æʱģ¿éVHDL³ÌÐò£¨JSQ.VHD£©
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JSQ IS
PORT (CLR, LDN, EN, CLK: IN STD_LOGIC;
TA, TB: IN STD_LOGIC;
QA: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
QB: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END JSQ;
ARCHITECTURE ART OF JSQ IS
SIGNAL DA: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL DB: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS (TA,TB,CLR)
BEGIN
IF CLR='1' THEN
DA<="0000";
DB<="0000";
ELSE
IF TA='1' THEN
DA<=DA+"0001" ;
END IF;
IF TB='1' THEN
DB<=DB+"0001";
END IF;
END IF;
END PROCESS;
