Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0
4 Freescale Semiconductor
43 CWM Cache write mode. When set to write-through mode, the W page attribute from an optional MMU is ignored
and all writes are treated as write through required. When set, write accesses are performed in copy-back
mode unless the W page attribute from an optional MMU is set.
0 Cache operates in write-through mode.
1 Cache operates in copy-back mode.
44 DPB Disable push buffer
0 Push buffer enabled
1 Push buffer disabled
45 DSB Disable store buffer
0 Store buffer enabled
1 Store buffer disabled
46 DSTRM Disable streaming
0 Streaming is enabled.
1 Streaming is disabled.
47 CPE Cache parity enable
0 Parity checking is disabled.
1 Parity checking is enabled.
48–52 — Reserved, should be cleared.
53 CUL Cache unable to lock. Indicates a lock set instruction was not effective in locking a cache line. This bit is set
by hardware on an “unable to lock” condition (other than lock overflows), and remain set until cleared by
software writing 0 to this bit location.
54 CLO Cache lock overflow. Indicates a lock overflow (overlocking) condition occurred. Set by hardware on an
overlocking condition, and remains set until cleared by software writing 0 to this bit location.
55 CLFC Cache lock bits flash clear. When written to a 1, a cache lock bits flash clear operation is initiated by
hardware. Once complete, this bit is reset to 0. Writing a 1 while a flash clear operation is in progress results
in an undefined operation. Writing a 0 to this bit while a flash clear operation is in progress has no effect.
Cache lock bits flash clear operations require approximately 134 cycles to complete. Clearing occurs
regardless of the enable (CE) value.
56–60 — Reserved, should be cleared.
61 CABT Cache operation aborted. Indicates a cache invalidate or a cache lock bits flash clear operation was aborted
prior to completion. Set by hardware on an aborted condition, and remains set until cleared by software
writing 0 to this bit location.
62 CINV Cache invalidate
0 No cache invalidate
1 Cache invalidation operation
When written to a 1, a cache invalidation operation is initiated by hardware. Then invalidation is complete,
CINV is reset to 0. Writing a 1 while invalidation is in progress causes an undefined operation. Writing a 0
to this bit while an invalidation operation is in progress is ignored. Cache invalidation operations require
approximately 134 cycles to complete. Invalidation occurs regardless of the enable (CE) value.
63 CE Cache enable. When disabled, cache lookups are not performed for normal load or store accesses.
Other L1CSR0 cache control operations are still available. Also, store buffer operation is not affected by CE.
0 Cache is disabled
1 Cache is enabled
Table 2-26. L1CSR0 Field Descriptions (continued)
Bits Name Description
_KINGKANG_2019-01-04评价了有没有积分呢，。。
小懒_2012-07-10对于开发很有帮助，可以快速的找到指令详解。。。
paigukai2011-09-08蛮不错的 看不懂汇编的时候可以快速查看
jobbyjobby2011-09-14好像没有中断相关指令。
hirofeng892015-06-10资源不错，清晰
