PowerPC(e200z6核)的汇编指令速查资源-CSDN文库

PowerPC

4星 · 超过85%的资源需积分: 50 195 浏览量 2009-07-17 20:15:50 上传评论收藏 141KB PDF 举报

资源推荐

资源详情

资源评论

Freescale Semiconductor

Addendum

This errata describes corrections to the e200z6 PowerPC™ Core Reference Manual, Revision 0. For

convenience, the section number and page number of the errata item in the reference manual are provided.

Items in bold are new since the last revision of this document.

To locate any published updates for this document, visit our website listed on the back cover of this

document.

Section, Page No. Changes

2.3.1, 2-8 Add the following to the description of MSR[EE]:

“If MSR[EE] = 0 and a transfer error occurs, a DSI or ISI is taken rather than a

machine check or checkstop, as defined by the PowerPC architecture. For more

information see the note in Section 5.6.2, “Machine Check Interrupt (IVOR1),”.

This does not affect the e200z6 with VLE.”

1. Which is provided in an erratum below.

Document Number: e200z6RMAD

Rev. 0.2, 10/2006

Errata to the

e200z6 PowerPC™ Core

Reference Manual, Rev. 0

Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0

Freescale Semiconductor 3

2.13.1, 2-55 Add WAM bit 42 to the L1 Cache Control and Status Register 0 (L1CSR0).

Replace Figure 2-40 and Table 2-26 with the following:

Way Partitioning APU Bits

32 35 36 39 40 41 42 43 44 45 46 47

Field WID WDD AWID AWDD WAM CWM DPB DSB DSTRM CPE

Reset All zeros

R/W R/W

Line Locking APU Bits

48 52 53 54 55 56 60 61 62 63

Field — CUL CLO CLFR — CABT CFI CE

Reset All zeros

R/W R/W

SPR SPR 1010

Figure 2-40. L1 Cache Control and Status Register 0 (L1CSR0)

Table 2-26. L1CSR0 Field Descriptions

Bits Name Description

32–35 WID Way instruction disable. WID and WDD are used for locking ways of the cache and determining the cache

replacement policy.

0 The corresponding way is available for replacement by instruction miss line fills.

1 The corresponding way is not available for replacement by instruction miss line fills.

Bit 0 corresponds to way 0, bit 1 corresponds to way 1, bit 2 corresponds to way 2, and

bit 3 corresponds to way 3.

36–39 WDD Way data disable. WID and WDD are used for locking ways of the cache and determining the cache

replacement policy.

0 The corresponding way is available for replacement by data miss line fills.

1 The corresponding way is not available for replacement by data miss line fills.

Bit 4 corresponds to way 0, bit 5 corresponds to way 1, bit 6 corresponds to way 2, bit 7 corresponds to

way 3.

40 AWID Additional ways instruction disable

0 Additional ways beyond 0–3 are available for replacement by instruction miss line fills.

1 Additional ways beyond 0–3 are not available for replacement by instruction miss line fills.

For the 32-Kbyte 8-way cache, ways 4–7 are considered additional ways.

41 AWDD Additional ways data disable

0 Additional ways beyond 0–3 are available for replacement by data miss line fills.

1 Additional ways beyond 0–3 are not available for replacement by data miss line fills.

For the 32-Kbyte 8-way cache, ways 4–7 are considered additional ways.

42 WAM Cache way partitioning APU. Way access mode.

0 All ways are available for access.

1 Only ways partitioned for the specific type of access are used for a fetch or read operation.

Errata to the e200z6 PowerPC™ Core Reference Manual, Rev. 0

4 Freescale Semiconductor

43 CWM Cache write mode. When set to write-through mode, the W page attribute from an optional MMU is ignored

and all writes are treated as write through required. When set, write accesses are performed in copy-back

mode unless the W page attribute from an optional MMU is set.

0 Cache operates in write-through mode.

1 Cache operates in copy-back mode.

44 DPB Disable push buffer

0 Push buffer enabled

1 Push buffer disabled

45 DSB Disable store buffer

0 Store buffer enabled

1 Store buffer disabled

46 DSTRM Disable streaming

0 Streaming is enabled.

1 Streaming is disabled.

47 CPE Cache parity enable

0 Parity checking is disabled.

1 Parity checking is enabled.

48–52 — Reserved, should be cleared.

53 CUL Cache unable to lock. Indicates a lock set instruction was not effective in locking a cache line. This bit is set

by hardware on an “unable to lock” condition (other than lock overflows), and remain set until cleared by

software writing 0 to this bit location.

54 CLO Cache lock overflow. Indicates a lock overflow (overlocking) condition occurred. Set by hardware on an

overlocking condition, and remains set until cleared by software writing 0 to this bit location.

55 CLFC Cache lock bits flash clear. When written to a 1, a cache lock bits flash clear operation is initiated by

hardware. Once complete, this bit is reset to 0. Writing a 1 while a flash clear operation is in progress results

in an undefined operation. Writing a 0 to this bit while a flash clear operation is in progress has no effect.

Cache lock bits flash clear operations require approximately 134 cycles to complete. Clearing occurs

regardless of the enable (CE) value.

56–60 — Reserved, should be cleared.

61 CABT Cache operation aborted. Indicates a cache invalidate or a cache lock bits flash clear operation was aborted

prior to completion. Set by hardware on an aborted condition, and remains set until cleared by software

writing 0 to this bit location.

62 CINV Cache invalidate

0 No cache invalidate

1 Cache invalidation operation

When written to a 1, a cache invalidation operation is initiated by hardware. Then invalidation is complete,

CINV is reset to 0. Writing a 1 while invalidation is in progress causes an undefined operation. Writing a 0

to this bit while an invalidation operation is in progress is ignored. Cache invalidation operations require

approximately 134 cycles to complete. Invalidation occurs regardless of the enable (CE) value.

63 CE Cache enable. When disabled, cache lookups are not performed for normal load or store accesses.

Other L1CSR0 cache control operations are still available. Also, store buffer operation is not affected by CE.

0 Cache is disabled

1 Cache is enabled

Table 2-26. L1CSR0 Field Descriptions (continued)

Bits Name Description

剩余23页未读，继续阅读

评论收藏

内容反馈

_KINGKANG_

2019-01-04

评价了有没有积分呢，。。
小懒_

2012-07-10

对于开发很有帮助，可以快速的找到指令详解。。。
paigukai

2011-09-08

蛮不错的看不懂汇编的时候可以快速查看
jobbyjobby

2011-09-14

好像没有中断相关指令。
hirofeng89

2015-06-10

资源不错，清晰

lc841004

粉丝: 2
资源: 5

PowerPC(e200z6核)的汇编指令速查

E200Z6-POWERPC参考手册

PowerPC指令集详解

e200_z7_use.pdf

E2006Z汇编指令指南

蜂鸟E200系列处理器SOC核开发教程

powerpc汇编指令手册

Powerpc 汇编指令速查

PowerPC汇编指令速查

汇编指令速查器

PowerPC汇编指令

很好用的汇编指令速查软件

e200z6.pdf

e200z0RM内核参考手册_参考手册；PowerPC_源码

powerpc-eabivle-4_9.rar

powerpc linux编程手册

飞思卡尔公司powerpc架构MPC5604B单片机全部例程.zip

汇编指令速查手册

《汇编指令速查手册》

PowerPC汇编指令.doc

MPC5744P-C中使用汇编_MPC5744P_

飞思卡尔 NXP MPC5604 MPC56xx powerpc超级详细的培训资料

MPC5744P_FreeRTOSV10_MPC5744FreeRTOS_powerpc_MPC5744P_freertos_f

e200z760RM.pdf

全志F1E200芯片手册

e200_master_hbirdkit:_fpga_verilog_E200_risc-vcpu_

RISC-V峰鸟E200源码.zip

PowerPC Lauterbach cmm: Halt the core directly at power on reset

最新资源