System Management Bus (SMBus) Specification Version 2.0
SBS Implementers Forum 1
System Management Bus
(SMBus)
Specification
Version 2.0
August 3, 2000
SBS Implementers Forum
Copyright
1994, 1995, 1998, 2000
Duracell, Inc., Energizer Power Systems, Inc., Fujitsu, Ltd., Intel Corporation, Linear Technology
Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc.,
Toshiba Battery Co. Ltd., Unitrode Corporation, USAR Systems, Inc.
All rights reserved.
System Management Bus (SMBus) Specification Version 2.0
SBS Implementers Forum 2
THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, WHETHER
EXPRESS
, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF
MERCHANTABILITY
, NONINFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE, OR
ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL
, SPECIFICATION OR SAMPLE.
I
N NO EVENT WILL ANY SPECIFICATION CO-OWNER BE LIABLE TO ANY OTHER PARTY FOR
ANY LOSS OF PROFITS
, LOSS OF USE, INCIDENTAL, CONSEQUENTIAL, INDIRECT OR SPECIAL
DAMAGES ARISING OUT OF THIS SPECIFICATION
, WHETHER OR NOT SUCH PARTY HAD
ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES
. FURTHER, NO WARRANTY OR
REPRESENTATION IS MADE OR IMPLIED RELATIVE TO FREEDOM FROM INFRINGEMENT OF
ANY THIRD PARTY PATENTS WHEN PRACTICING THE SPECIFICATION
.
* Other product and corporate names may be trademarks of other companies and are used
only for explanation and to the owner’s benefit, without intent to infringe.
Revision No. Date Notes
1.0 2/15/95 General Release
1.1 12/11/98 Version 1.1 Release
2.0 8/3/00 Version 2.0 Release
Questions and comments regarding this
specification may be forwarded to:
questions@sbs-forum.org
For additional information on Smart
Battery System Specifications, visit the
SBS Implementer’s Forum (SBS-IF) at:
www.sbs-forum.org
System Management Bus (SMBus) Specification Version 2.0
SBS Implementers Forum 3
Table of Contents
1. INTRODUCTION................................................................................................................... 5
1.1. Overview............................................................................................................................................ 5
1.2. Audience ............................................................................................................................................ 5
1.3. Scope .................................................................................................................................................. 5
1.4. Organization of this document......................................................................................................... 5
1.5. Supporting documents...................................................................................................................... 6
1.6. Definitions of terms........................................................................................................................... 6
1.7. Conventions ....................................................................................................................................... 8
2. GENERAL CHARACTERISTICS ......................................................................................... 9
3. LAYER 1 – THE PHYSICAL LAYER ................................................................................. 11
3.1. Electrical characteristics of SMBus devices – two discrete worlds............................................. 11
3.1.1. SMBus common AC specifications .......................................................................................... 11
3.1.2. Low-power DC specifications................................................................................................... 14
3.1.3. High-Power DC specifications.................................................................................................. 16
3.1.4 Additional common low and high-power specifications........................................................... 17
4. LAYER 2 – THE DATA LINK LAYER ................................................................................ 18
4.1. Bit transfers..................................................................................................................................... 18
4.1.1. Data validity.............................................................................................................................. 18
4.1.2. START and STOP conditions................................................................................................... 18
4.1.3. Bus idle condition ..................................................................................................................... 18
4.2. Data transfers on SMBus ............................................................................................................... 19
4.3. Clock generation and arbitration .................................................................................................. 20
4.3.1. Synchronization ........................................................................................................................ 20
4.3.2. Arbitration................................................................................................................................. 21
4.3.3. Clock low extending ................................................................................................................. 22
4.4. Data transfer formats ..................................................................................................................... 23
5. LAYER 3 – NETWORK LAYER ......................................................................................... 24
5.1. Usage model..................................................................................................................................... 24
5.2. Device identification – slave address ............................................................................................. 24
5.2.1. SMBus address types ................................................................................................................ 25
5.3. Using a device .................................................................................................................................. 26
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5.4.
Packet error checking..................................................................................................................... 26
5.4.1. Packet error checking implementation...................................................................................... 26
5.5. Bus Protocols................................................................................................................................... 27
5.5.1. Quick command........................................................................................................................ 28
5.5.2. Send byte................................................................................................................................... 29
5.5.3. Receive byte.............................................................................................................................. 29
5.5.4. Write byte/word ........................................................................................................................ 29
5.5.5. Read byte/word......................................................................................................................... 30
5.5.6. Process call ...............................................................................................................................31
5.5.7. Block write/read........................................................................................................................ 31
5.5.8. Block write-block read process call .......................................................................................... 32
5.5.9 SMBus host notify protocol ......................................................................................................34
5.6. SMBus Address resolution protocol.............................................................................................. 34
5.6.1. Unique Device Identifier (UDID) ............................................................................................. 34
5.6.2. Power-on reset .......................................................................................................................... 38
5.6.3. ARP commands ........................................................................................................................ 38
APPENDIX A – OPTIONAL SMBUS SIGNALS ........................................................................... 54
SMBSUS# .................................................................................................................................................... 54
SMBALERT#.............................................................................................................................................. 55
APPENDIX B – DIFFERENCES BETWEEN SMBUS AND I
2
C ................................................... 57
DC specifications for SMBus and I2C....................................................................................................... 57
Timing specification differences between SMBus and I
2
C...................................................................... 58
Other differences......................................................................................................................................... 58
APPENDIX C – SMBUS DEVICE ADDRESS ASSIGNMENTS ................................................... 59
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1. Introduction
1.1. Overview
The System Management Bus (SMBus) is a two-wire interface through which various system component
chips can communicate with each other and with the rest of the system. It is based on the principles of
operation of I
2
C
*
.
SMBus provides a control bus for system and power management related tasks. A system may use SMBus
to pass messages to and from devices instead of tripping individual control lines. Removing the individual
control lines reduces pin count. Accepting messages ensures future expandability.
With System Management Bus, a device can provide manufacturer information, tell the system what its
model/part number is, save its state for a suspend event, report different types of errors, accept control
parameters, and return its status.
1.2. Audience
The target audience for this document includes but is not limited to:
• System designers implementing the System Management Bus Specification in their systems
• VLSI engineers designing chips to connect to the System Management Bus
• Software engineers writing support code for System Management Bus chips
1.3. Scope
This document describes the electrical characteristics, network control conventions and communications
protocols used by SMBus devices. These can be thought as existing at the first three layers of the seven-
layer OSI network model, that is, the physical, data link and network layers. Functions normally
implemented at higher layers of the OSI model are beyond the scope of this document.
The original purpose of the SMBus was to define the communication link between an intelligent battery, a
charger for the battery and a microcontroller that communicates with the rest of the system. However,
SMBus can also be used to connect a wide variety of devices including power-related devices, system
sensors, inventory EEPROMs communications devices and more.
This version of the specification is a superset of previous versions, 1.0 and 1.1. All devices compliant with
these previous versions are compliant with this version. Those features new to SMBus with this version of
the spec are optional and are appropriate to the new environments enabled by those features. However, if
implemented, these new features must be implemented in a manner compliant with this specification.
1.4. Organization of this document
This document is organized to first give the reader an overview of the SMBus and then to delve deeper into
its actual working. The major technical discussion appears in three sections that treat the various aspects of
the SMBus as they would appear in the first three layers of the OSI reference network model, the physical
layer the data link layer and the network layer.
The section on the physical layer sets out SMBus electrical characteristics. The section on the data link
layer specifies bit transfers, byte data transfers, arbitration and clock signals. The section on the link layer
deals with the general usage model, the concept of addresses in SMBus, the Address Resolution Protocol
and the bus data transfer protocol. All aspects of the SMBus proper may be described within the scope of
the first three OSI layers.
The SMBus is a multiple attachment bus with no routing capability. Most communication occurs between
and involves only two nodes, a master and a slave. Exceptions to this rule occur during and apply to
devices that implement the Address Resolution Protocol as well as the Alert Response Address.
