CDI / IBL #: 376562 Intel Confidential 5
5.14.1 Theory of Operation.............................................................................. 178
5.14.2 TCO Modes.......................................................................................... 179
5.15 General Purpose I/O (D31:F0) .......................................................................... 182
5.15.1 Power Wells......................................................................................... 182
5.15.2 SMI# and SCI Routing .......................................................................... 183
5.15.3 Triggering ........................................................................................... 183
5.15.4 GPIO Registers Lockdown...................................................................... 183
5.15.5 Serial POST Codes Over GPIO................................................................ 183
5.15.6 Management Engine GPIOs.................................................................... 186
5.16 SATA Host Controller (D31:F2, F5) .................................................................... 186
5.16.1 SATA Feature Support........................................................................... 187
5.16.2 Theory of Operation.............................................................................. 188
5.16.3 SATA Swap Bay Support ....................................................................... 188
5.16.4 Hot Plug Operation ............................................................................... 188
5.16.5 Function Level Reset Support (FLR) ........................................................ 189
5.16.6 Intel
®
Matrix Storage Technology Configuration ....................................... 190
5.16.7 Power Management Operation................................................................ 191
5.16.8 SATA Device Presence........................................................................... 193
5.16.9 SATA LED............................................................................................ 193
5.16.10AHCI Operation.................................................................................... 193
5.16.11Serial ATA Reference Clock Low Power Request (SATACLKREQ#)................ 194
5.16.12SGPIO Signals ..................................................................................... 194
5.16.13External SATA...................................................................................... 199
5.17 High Precision Event Timers.............................................................................. 199
5.17.1 Timer Accuracy.................................................................................... 199
5.17.2 Interrupt Mapping ................................................................................ 199
5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 200
5.17.4 Enabling the Timers.............................................................................. 201
5.17.5 Interrupt Levels ................................................................................... 201
5.17.6 Handling Interrupts .............................................................................. 201
5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors.............................. 202
5.18 USB UHCI Host Controllers (D29:F0, F1, F2, F3 and D26:F0, F1 and F2)................. 202
5.18.1 Data Structures in Main Memory............................................................. 202
5.18.2 Data Transfers to/from Main Memory...................................................... 202
5.18.3 Data Encoding and Bit Stuffing............................................................... 203
5.18.4 Bus Protocol ........................................................................................ 203
5.18.5 Packet Formats.................................................................................... 203
5.18.6 USB Interrupts..................................................................................... 204
5.18.7 USB Power Management ....................................................................... 206
5.18.8 USB Legacy Keyboard Operation ............................................................ 207
5.18.9 Function Level Reset Support (FLR) ........................................................ 210
5.19 USB EHCI Host Controllers (D29:F7 and D26:F7)................................................. 211
5.19.1 EHC Initialization.................................................................................. 211
5.19.2 Data Structures in Main Memory............................................................. 212
5.19.3 USB 2.0 Enhanced Host Controller DMA................................................... 212
5.19.4 Data Encoding and Bit Stuffing............................................................... 212
5.19.5 Packet Formats.................................................................................... 213
5.19.6 USB 2.0 Interrupts and Error Conditions.................................................. 213
5.19.7 USB 2.0 Power Management.................................................................. 214
5.19.8 Interaction with UHCI Host Controllers .................................................... 215
5.19.9 USB 2.0 Legacy Keyboard Operation....................................................... 218
5.19.10USB 2.0 Based Debug Port .................................................................... 219
5.19.11USB Pre-Fetch Based Pause................................................................... 223
5.19.12Function Level Reset Support (FLR) ........................................................ 223
5.20 SMBus Controller (D31:F3)............................................................................... 224
5.20.1 Host Controller..................................................................................... 225
5.20.2 Bus Arbitration..................................................................................... 229
5.20.3 Bus Timing.......................................................................................... 229
5.20.4 Interrupts / SMI#................................................................................. 230
5.20.5 SMBALERT# ........................................................................................ 231
5.20.6 SMBus CRC Generation and Checking...................................................... 231
5.20.7 SMBus Slave Interface.......................................................................... 231
5.21 Intel
®
High Definition Audio Overview................................................................ 238
5.22 Intel
®
Active Management Technology (Intel
®
AMT)............................................ 238
5.22.1 Intel
®
AMT Features............................................................................. 238
5.22.2 Intel
®
AMT Requirements...................................................................... 239
5.23 Serial Peripheral Interface (SPI)........................................................................ 239
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