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### Intel I/O Controller Hub 10 (ICH10) Family：关键知识点解析 #### 一、概述 Intel I/O Controller Hub 10 (ICH10) 是一款由英特尔公司设计和制造的芯片组组件，主要负责处理计算机系统中的输入/输出（I/O）功能。ICH10 被广泛应用于各种基于Intel平台的个人电脑和工作站中，提供包括USB、SATA、音频等在内的多种接口和支持。本文将深入探讨ICH10的关键技术特点和应用领域。 #### 二、外部设计规格（EDS） ICH10的外部设计规格文档详细介绍了该芯片组的设计规范和技术参数，是开发人员进行硬件设计的重要参考。该文档通常包含以下内容： 1. **总览**：介绍ICH10的基本架构和功能。 2. **接口规格**：详细说明了各个I/O接口的技术参数，如USB、SATA等。 3. **电气特性**：提供了各引脚的电气特性，帮助设计人员确保信号完整性和电源管理。 4. **机械特性**：包括尺寸、安装孔位置等信息，确保与主板及其他组件的兼容性。 5. **热设计**：给出了散热解决方案的建议，确保芯片在工作时不会过热。 6. **可靠性与测试**：介绍了芯片的可靠性测试方法和标准。 #### 三、技术特点 1. **USB支持**：ICH10 支持多个高速USB端口，为用户提供高速数据传输能力。 2. **SATA接口**：提供SATA 3.0Gb/s接口，支持高速硬盘读写操作。 3. **音频支持**：内置音频控制器，支持多通道高保真音频输出。 4. **网络功能**：通过集成的网络控制器支持千兆以太网连接。 5. **PCI Express**：支持PCI Express总线，用于连接高性能显卡和其他扩展卡。 6. **I2C/SMBus**：支持I2C和SMBus协议，用于监控和管理系统的温度、电压等状态信息。 7. **电源管理**：采用先进的电源管理模式，实现高效能和低功耗。 #### 四、应用场景 1. **个人电脑**：ICH10被广泛应用于桌面级个人电脑中，为其提供丰富的I/O接口和强大的性能。 2. **工作站**：在需要高性能计算和大量数据传输的工作站中，ICH10能够满足专业用户的高要求。 3. **服务器**：对于小型服务器或入门级服务器来说，ICH10提供的稳定性和可靠性是非常重要的。 4. **嵌入式系统**：在某些特定的嵌入式应用场景下，ICH10也能发挥其优势，比如工业控制设备等。 #### 五、注意事项 1. **许可证**：使用ICH10及其相关技术时，需要注意是否需要获取必要的许可，例如I2C/SMBus的使用可能涉及专利权问题。 2. **兼容性**：确保ICH10与其他硬件组件之间的兼容性，特别是在设计阶段就要考虑到未来可能的升级需求。 3. **技术支持**：在开发过程中遇到问题时，可以联系当地的英特尔销售办公室或分销商获得技术支持。 4. **安全性**：考虑使用Intel® Active Management Technology等技术提高系统的安全性和可管理性。 5. **虚拟化支持**：对于需要支持虚拟化的应用场景，确保系统配置能够满足Intel® Virtualization Technology的要求。 Intel I/O Controller Hub 10 (ICH10)作为一款高度集成的芯片组，在计算机系统中扮演着非常重要的角色。通过对上述关键技术点的了解，开发者能够更好地利用ICH10的各项功能来构建高效稳定的硬件系统。

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Document Number: CDI / IBL #: 376562

Intel

I/O Controller Hub 10

(ICH10) Family

External Design Specification (EDS) - Volume 1 of 2

Revision 1.0

November 2007

Intel Confidential

2 Intel Confidential CDI / IBL #: 376562

Legal Lines and Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL

PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for

use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

I/O Controller Hub 10 (ICH10) Family chipset component may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I

C bus/protocol and was developed by Intel.

Implementations of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Intel

Active Management Technology requires the computer have a 945G chipset and a PRO/1000PM, be plugged into a power source, and have a

network connection.

± Intel

Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some uses,

certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on hardware and software configurations. Intel

Virtualization Technology-enabled VMM applications are currently in development.

Intel, Intel SpeedStep, Intel Viiv, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States

and other countries.

*Other names and brands may be claimed as the property of others.

CDI / IBL #: 376562 Intel Confidential 3

Contents

1Introduction............................................................................................................35

1.1 About This Manual.............................................................................................35

1.2 Overview .........................................................................................................39

1.2.1 Capability Overview................................................................................41

1.3 Intel

ICH10 SKU Definition ...............................................................................47

2 Signal Description ...................................................................................................49

2.1 Direct Media Interface (DMI) to Host Controller.....................................................51

2.2 PCI Express* ....................................................................................................52

2.3 LAN Connect Interface .......................................................................................52

2.4 Gigabit LAN Connect Interface ............................................................................53

2.5 Firmware Hub Interface......................................................................................54

2.6 PCI Interface ....................................................................................................55

2.7 Serial ATA Interface...........................................................................................57

2.8 LPC Interface....................................................................................................60

2.9 Interrupt Interface ............................................................................................61

2.10 USB Interface...................................................................................................62

2.11 Power Management Interface..............................................................................64

2.12 Processor Interface............................................................................................67

2.13 SMBus Interface................................................................................................68

2.14 System Management Interface............................................................................69

2.15 Real Time Clock Interface...................................................................................70

2.16 Other Clocks.....................................................................................................71

2.17 Miscellaneous Signals ........................................................................................71

2.18 Intel® High Definition Audio Link ........................................................................72

2.19 Serial Peripheral Interface (SPI)..........................................................................73

2.20 Controller Link..................................................................................................74

2.21 Intel® Quiet System Technology.........................................................................74

2.22 JTAG Signals (ICH10 Corporate Family Only) ........................................................75

2.23 General Purpose I/O Signals ...............................................................................75

2.24 Power and Ground Signals..................................................................................78

2.25 Pin Straps ........................................................................................................81

2.25.1 Functional Straps ...................................................................................81

2.25.2 External RTC Circuitry.............................................................................85

2.26 Device and Revision ID Table..............................................................................86

3Intel

ICH10 Pin States...........................................................................................89

3.1 Integrated Pull-Ups and Pull-Downs.....................................................................89

3.2 Output and I/O Signals Planes and States.............................................................91

3.3 Power Planes for Input Signals............................................................................97

4Intel

ICH10 and System Clock Domains............................................................... 101

5 Functional Description........................................................................................... 103

5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 103

5.1.1 PCI Bus Interface ................................................................................. 103

5.1.2 PCI Bridge As an Initiator...................................................................... 103

5.1.3 Parity Error Detection and Generation ..................................................... 105

5.1.4 PCIRST#............................................................................................. 106

5.1.5 Peer Cycles ......................................................................................... 106

5.1.6 PCI-to-PCI Bridge Model........................................................................ 106

5.1.7 IDSEL to Device Number Mapping .......................................................... 107

5.1.8 Standard PCI Bus Configuration Mechanism ............................................. 107

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)................................................ 107

5.2.1 Interrupt Generation............................................................................. 107

5.2.2 Power Management .............................................................................. 108

5.2.3 SERR# Generation ............................................................................... 109

5.2.4 Hot-Plug ............................................................................................. 110

5.3 Gigabit Ethernet Controller (B0:D25:F0)............................................................. 111

5.3.1 Gigabit Ethernet PCI Bus Interface.......................................................... 112

5.3.2 Error Events and Error Reporting............................................................ 113

5.3.3 Ethernet Interface................................................................................ 113

5.3.4 PCI Power Management ........................................................................ 114

4 Intel Confidential CDI / IBL #: 376562

5.3.5 Configurable LEDs.................................................................................115

5.3.6 Function Level Reset Support (FLR).........................................................116

5.4 LPC Bridge (w/ System and Management Functions) (D31:F0)...............................117

5.4.1 LPC Interface .......................................................................................117

5.5 DMA Operation (D31:F0) ..................................................................................123

5.5.1 Channel Priority....................................................................................124

5.5.2 Address Compatibility Mode ...................................................................124

5.5.3 Summary of DMA Transfer Sizes.............................................................125

5.5.4 Autoinitialize........................................................................................125

5.5.5 Software Commands.............................................................................126

5.6 LPC DMA ........................................................................................................126

5.6.1 Asserting DMA Requests........................................................................126

5.6.2 Abandoning DMA Requests.....................................................................127

5.6.3 General Flow of DMA Transfers...............................................................127

5.6.4 Terminal Count.....................................................................................128

5.6.5 Verify Mode .........................................................................................128

5.6.6 DMA Request Deassertion......................................................................128

5.6.7 SYNC Field / LDRQ# Rules .....................................................................129

5.7 8254 Timers (D31:F0)......................................................................................130

5.7.1 Timer Programming ..............................................................................130

5.7.2 Reading from the Interval Timer.............................................................131

5.8 8259 Interrupt Controllers (PIC) (D31:F0)...........................................................133

5.8.1 Interrupt Handling ................................................................................134

5.8.2 Initialization Command Words (ICWx) .....................................................135

5.8.3 Operation Command Words (OCW) .........................................................136

5.8.4 Modes of Operation...............................................................................136

5.8.5 Masking Interrupts................................................................................139

5.8.6 Steering PCI Interrupts..........................................................................139

5.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0)...............................140

5.9.1 Interrupt Handling ................................................................................140

5.9.2 Interrupt Mapping.................................................................................140

5.9.3 PCI / PCI Express* Message-Based Interrupts ..........................................141

5.9.4 Front Side Bus Interrupt Delivery............................................................141

5.9.5 IOxAPIC Address Remapping..................................................................143

5.9.6 External Interrupt Controller Support ......................................................143

5.10 Serial Interrupt (D31:F0)..................................................................................144

5.10.1 Start Frame .........................................................................................144

5.10.2 Data Frames........................................................................................145

5.10.3 Stop Frame..........................................................................................145

5.10.4 Specific Interrupts Not Supported via SERIRQ...........................................145

5.10.5 Data Frame Format...............................................................................146

5.11 Real Time Clock (D31:F0).................................................................................147

5.11.1 Update Cycles ......................................................................................147

5.11.2 Interrupts............................................................................................148

5.11.3 Lockable RAM Ranges............................................................................148

5.11.4 Century Rollover...................................................................................148

5.11.5 Clearing Battery-Backed RTC RAM...........................................................148

5.12 Processor Interface (D31:F0) ............................................................................150

5.12.1 Processor Interface Signals ....................................................................150

5.12.2 This active-low signal controls the internal gating of the processor’s core clock.

This signal asserts before and deasserts after the STP_CPU# signal to effectively

stop the processor’s clock (internally) in the states in which STP_CPU# can be

used to stop the processor’s clock externally.Dual-Processor Issues152

5.13 Power Management (D31:F0)............................................................................154

5.13.1 Features..............................................................................................154

5.13.2 Intel

ICH10 and System Power States ...................................................154

5.13.3 System Power Planes ............................................................................156

5.13.4 SMI#/SCI Generation............................................................................157

5.13.5 Dynamic Processor Clock Control ............................................................160

5.13.6 Sleep States ........................................................................................163

5.13.7 Thermal Management............................................................................166

5.13.8 Event Input Signals and Their Usage .......................................................167

5.13.9 ALT Access Mode..................................................................................170

5.13.10System Power Supplies, Planes, and Signals.............................................174

5.13.11Clock Generators..................................................................................176

5.13.12Legacy Power Management Theory of Operation .......................................177

5.14 System Management (D31:F0)..........................................................................178

CDI / IBL #: 376562 Intel Confidential 5

5.14.1 Theory of Operation.............................................................................. 178

5.14.2 TCO Modes.......................................................................................... 179

5.15 General Purpose I/O (D31:F0) .......................................................................... 182

5.15.1 Power Wells......................................................................................... 182

5.15.2 SMI# and SCI Routing .......................................................................... 183

5.15.3 Triggering ........................................................................................... 183

5.15.4 GPIO Registers Lockdown...................................................................... 183

5.15.5 Serial POST Codes Over GPIO................................................................ 183

5.15.6 Management Engine GPIOs.................................................................... 186

5.16 SATA Host Controller (D31:F2, F5) .................................................................... 186

5.16.1 SATA Feature Support........................................................................... 187

5.16.2 Theory of Operation.............................................................................. 188

5.16.3 SATA Swap Bay Support ....................................................................... 188

5.16.4 Hot Plug Operation ............................................................................... 188

5.16.5 Function Level Reset Support (FLR) ........................................................ 189

5.16.6 Intel

Matrix Storage Technology Configuration ....................................... 190

5.16.7 Power Management Operation................................................................ 191

5.16.8 SATA Device Presence........................................................................... 193

5.16.9 SATA LED............................................................................................ 193

5.16.10AHCI Operation.................................................................................... 193

5.16.11Serial ATA Reference Clock Low Power Request (SATACLKREQ#)................ 194

5.16.12SGPIO Signals ..................................................................................... 194

5.16.13External SATA...................................................................................... 199

5.17 High Precision Event Timers.............................................................................. 199

5.17.1 Timer Accuracy.................................................................................... 199

5.17.2 Interrupt Mapping ................................................................................ 199

5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 200

5.17.4 Enabling the Timers.............................................................................. 201

5.17.5 Interrupt Levels ................................................................................... 201

5.17.6 Handling Interrupts .............................................................................. 201

5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors.............................. 202

5.18 USB UHCI Host Controllers (D29:F0, F1, F2, F3 and D26:F0, F1 and F2)................. 202

5.18.1 Data Structures in Main Memory............................................................. 202

5.18.2 Data Transfers to/from Main Memory...................................................... 202

5.18.3 Data Encoding and Bit Stuffing............................................................... 203

5.18.4 Bus Protocol ........................................................................................ 203

5.18.5 Packet Formats.................................................................................... 203

5.18.6 USB Interrupts..................................................................................... 204

5.18.7 USB Power Management ....................................................................... 206

5.18.8 USB Legacy Keyboard Operation ............................................................ 207

5.18.9 Function Level Reset Support (FLR) ........................................................ 210

5.19 USB EHCI Host Controllers (D29:F7 and D26:F7)................................................. 211

5.19.1 EHC Initialization.................................................................................. 211

5.19.2 Data Structures in Main Memory............................................................. 212

5.19.3 USB 2.0 Enhanced Host Controller DMA................................................... 212

5.19.4 Data Encoding and Bit Stuffing............................................................... 212

5.19.5 Packet Formats.................................................................................... 213

5.19.6 USB 2.0 Interrupts and Error Conditions.................................................. 213

5.19.7 USB 2.0 Power Management.................................................................. 214

5.19.8 Interaction with UHCI Host Controllers .................................................... 215

5.19.9 USB 2.0 Legacy Keyboard Operation....................................................... 218

5.19.10USB 2.0 Based Debug Port .................................................................... 219

5.19.11USB Pre-Fetch Based Pause................................................................... 223

5.19.12Function Level Reset Support (FLR) ........................................................ 223

5.20 SMBus Controller (D31:F3)............................................................................... 224

5.20.1 Host Controller..................................................................................... 225

5.20.2 Bus Arbitration..................................................................................... 229

5.20.3 Bus Timing.......................................................................................... 229

5.20.4 Interrupts / SMI#................................................................................. 230

5.20.5 SMBALERT# ........................................................................................ 231

5.20.6 SMBus CRC Generation and Checking...................................................... 231

5.20.7 SMBus Slave Interface.......................................................................... 231

5.21 Intel

High Definition Audio Overview................................................................ 238

5.22 Intel

Active Management Technology (Intel

AMT)............................................ 238

5.22.1 Intel

AMT Features............................................................................. 238

5.22.2 Intel

AMT Requirements...................................................................... 239

5.23 Serial Peripheral Interface (SPI)........................................................................ 239

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2014-05-29

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