ARM7 NandFlash读写【采用EBI】

/************************************************************************/ /* 文 件 名： nandflash.c */ /* 文件说明： nandflash 底层驱动函数 */ /* 编 写 人： 杨驌宇 */ /* 编写日期： [11/14/2008] */ /* 版权所有： 华中科技大学Dian团队ARM7组 */ /************************************************************************/ #include "../inc/AT91SAM7SE512.h" #include "../inc/nandflash.h" extern void AT91F_EBI_NandFlash_CfgPIO(void) { //>!Enable PMC clock AT91C_BASE_PMC->PMC_PCER = (1<<PIOA_ID) | (1<<PIOC_ID) ; //>!Assign them as EBI AT91C_BASE_PIOC->PIO_PDR = NAND_BUS | PIO_NAND_CLE | PIO_NAND_ALE | PIO_NAND_OE | PIO_NAND_WE | EBI_NCS3 ; AT91C_BASE_PIOC->PIO_OER = NAND_BUS | PIO_NAND_CLE | PIO_NAND_ALE | PIO_NAND_OE | PIO_NAND_WE | EBI_NCS3 ; AT91C_BASE_PIOC->PIO_ASR = NAND_BUS | PIO_NAND_CLE | PIO_NAND_ALE ; AT91C_BASE_PIOC->PIO_BSR = PIO_NAND_OE | PIO_NAND_WE | EBI_NCS3 ; //>!Assign NAND_STAUS & NAND_CHIPEN as normal PIO AT91C_BASE_PIOA->PIO_PER = NAND_STAUS; AT91C_BASE_PIOA->PIO_OER = NAND_STAUS; AT91C_BASE_PIOA->PIO_SODR= NAND_STAUS; AT91C_BASE_PIOB->PIO_PER = NAND_CHIPEN; AT91C_BASE_PIOB->PIO_OER = NAND_CHIPEN; // Disable Pull ups on A21/NANDALE and A22/NANDCLE AT91C_BASE_PIOC -> PIO_PPUDR = ((PIO_NAND_CLE) | (PIO_NAND_ALE)); //Add but not as same as offical code return; } extern void AT91F_NandFlash_Init (void) { //>!Enable NandFlash Logic AT91C_BASE_EBI->EBI_CSA = ((AT91C_BASE_EBI->EBI_CSA)|(EBI_CSA3)); //>!Config SMC_CSR3 AT91C_BASE_SMC->SMC2_CSR[3] = AT91C_SMC2_NWS_2 | AT91C_SMC2_WSEN_EN | AT91C_SMC2_TDF_2_CYCLES | AT91C_SMC2_BAT_8BIT | AT91C_SMC2_DBW_8 | AT91C_SMC2_DRP_STANDARD | AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_RWSETUP_0_CYCLE | AT91C_SMC2_RWHOLD_1_CYCLE ; // 2 wait states required required by the NAND Flash device // NWS register enabled // 2 Data Float Time Cycles required by the NAND Flash device // 1 8-bit device connected over the bus // 8-bit Data Bus Width // Standard Read protocol required by the NAND Flash device // Standard address to chip select // 0 Read/Write Setup time required by the Nand Flash Device // 1 Read/Write Setup time required by the ECC controller; //>!Config PIO AT91F_EBI_NandFlash_CfgPIO(); //>!Flash Enable NAND_ENABLE_CE(); return; } extern char AT91F_NandFlash_Char_Read(unsigned long addr) { unsigned long i=3; unsigned char result; addr = addr&0x3fffffff; //>!Flash Enable NAND_ENABLE_CE(); WRITE_NAND_COMMAND(NAND_CMD_READ1); WRITE_NAND_ADDRESS(addr); addr = (addr>>8); WRITE_NAND_ADDRESS((addr&0x0f)); //>! Only can send last 4 bit addr = (addr>>4); do { WRITE_NAND_ADDRESS(addr); addr = (addr>>8); } while(--i); WRITE_NAND_COMMAND(NAND_CMD_READ2); NAND_WAIT_READY(); // Wait for Read/Busy Signal assertion //Dead Loop result = READ_NAND(); //NAND_DISABLE_CE(); return result; } extern void AT91F_NandFlash_Char_Write(unsigned long addr,char value) { addr = addr&0x3fffffff; NAND_ENABLE_CE(); // Enable the NAND Flash device WRITE_NAND_COMMAND(NAND_CMD_PAGEPROG1); // Page Program Command 1 WRITE_NAND_ADDRESS(addr); addr = (addr>>8); WRITE_NAND_ADDRESS((addr&0x0f)); //>! Only can send last 4 bit addr = (addr>>4); WRITE_NAND_ADDRESS(addr); // Row address WRITE_NAND_ADDRESS(addr >> 8); // Row address WRITE_NAND_ADDRESS(addr >> 16); // Row address WRITE_NAND(value); WRITE_NAND_COMMAND(NAND_CMD_PAGEPROG2); // Page Program Command 2 addr = addr<<1; //For delay addr = addr>>1; //For delay NAND_WAIT_READY(); // Wait for Read/Busy Signal assertion //NAND_DISABLE_CE(); return; } int AT91F_NandFlash_Block_Erase(unsigned int block_num) { int Delay=0; block_num = block_num&0x03ffff; //UINT Addr = (UINT)(block_num*32*3); /* //擦写对应块的ECC for(i=0;i<PAGES_PRE_BLOCK*3;i++) { EEPROM_ByteWrite((Addr&0xFF00)>>8,(BYTE)(Addr&0x00FF),0xff); Addr++; } */ WRITE_NAND_COMMAND(NAND_CMD_ERASE1); WRITE_NAND_ADDRESS(block_num); WRITE_NAND_ADDRESS(block_num>> 8); //3 cycles WRITE_NAND_ADDRESS(block_num>>16); WRITE_NAND_COMMAND(NAND_CMD_ERASE2); Delay ++; // 等待至少100ns for(Delay = 0; Delay < TIMEOUT_ERASE_BLOCK+3; Delay ++) { if(Delay >= TIMEOUT_ERASE_BLOCK) return 1; //等待超时 } NAND_WAIT_READY(); return 0; //return !(nand_flash_read_status() & NAND_STATUS_ERROR); } int AT91F_NandFlash_Read_ID (unsigned char * maker,unsigned char * device) { unsigned char Device=0,Maker=0; WRITE_NAND_COMMAND(NAND_CMD_READID); WRITE_NAND_ADDRESS(0x00); //执行完上一句后在执行本句 IO口全部是高电平 *maker = READ_NAND(); *device = READ_NAND(); Maker = READ_NAND(); Device= READ_NAND(); return 0; } extern void AT91F_NandFlash_Reset (void) { WRITE_NAND_COMMAND(NAND_CMD_RESET); return; } unsigned char AT91F_NandFlash_Status_Read(void) { unsigned char status=0; WRITE_NAND_COMMAND(NAND_CMD_STATUS); status = READ_NAND(); return status; } int AT91F_NandFlash_Page_Write(unsigned long page_num,unsigned long start_column,unsigned char *word_write,unsigned long write_length) { unsigned long i=write_length; unsigned char content = 0; page_num = page_num&0x03ffff; start_column = start_column&0x0fff; NAND_ENABLE_CE(); // Enable the NAND Flash device WRITE_NAND_COMMAND(NAND_CMD_PAGEPROG1); // Page Program Command 1 WRITE_NAND_ADDRESS(start_column); WRITE_NAND_ADDRESS(start_column>>8); //>! Only can send last 4 bit WRITE_NAND_ADDRESS(page_num); // Row address WRITE_NAND_ADDRESS(page_num >> 8); // Row address WRITE_NAND_ADDRESS(page_num >> 16); // Row address do{ content = *(word_write+write_length-i); WRITE_NAND(content); }while(--i); WRITE_NAND_COMMAND(NAND_CMD_PAGEPROG2); // Page Program Command 2 page_num = page_num<<1; //For delay page_num = page_num>>1; //For delay NAND_WAIT_READY(); // Wait for Read/Busy Signal assertion //NAND_DISABLE_CE(); content = AT91F_NandFlash_Status_Read(); if(0 == (0x01&content)){ return 0; //done } else{ return 1; //error } } int AT91F_NandFlash_Page_Read(unsigned long page_num,unsigned long start_column,unsigned char *word_read,unsigned long read_length) { unsigned long i = read_length; unsigned char content=0; page_num = page_num&0x03ffff; start_column = start_column&0x0fff; NAND_ENABLE_CE(); // Enable the NAND Flash device WRITE_NAND_COMMAND(NAND_CMD_READ1); //Read page Command 1