IR2136是功率MOSFET和IGBT专用栅极集成驱动电路

ir2136

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IR213(6,62,63,65,66,67,68)(J&S) & PbF

3-PHASE BRIDGE DRIVER

Packages

Description

The IR2136x (J&S) are high voltage, high

speed power MOSFET and IGBT drivers with

three independent high and low side

referenced output channels for 3-phase

applications. Proprietary HVIC technology

enables ruggedized monolithic construction.

Logic inputs are compatible with CMOS or

LSTTL outputs, down to 3.3 V logic. A current

trip function which terminates all six outputs

can be derived from an external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An

open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. Overcurrent fault

conditions are cleared automatically after a delay programmed externally via an RC network connected to the RCIN input. The output

drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to

simplify use in high frequency applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the

high side configuration which operates up to 600 V.

Part IR2136 IR21362 IR21363 IR21365 IR21366 IR21367 IR21368

Input Logic

___ ___

HIN, LIN

___

HIN, LIN

___ ___

HIN, LIN

___ ___

HIN, LIN

___ ___

HIN, LIN

___ ___

HIN, LIN

___ ___

HIN, LIN

Ton (typ.) 400 ns 400 ns 400 ns 400 ns 250 ns 250 ns 400 ns

Toff (typ.) 380ns 380 ns 380 ns 380 ns 180 ns 180 ns 380 ns

(typ.) 2.7 V 2.7 V 2.7 V 2.7 V 2.0 V 2.0 V 2.0 V

(typ.) 1.7 V 1.7 V 1.7 V 1.7 V 1.3 V 1.3 V 1.3 V

Vitrip+ 0.46 V 0.46 V 0.46 V 4.3 V 0.46 V 4.3 V 4.3 V

UVCC/BS+ 8.9 V 10.4 V 11.2 V 11.2 V 11.2 V 11.2 V 8.9 V

UVCC/BS- 8.2 V 9.4 V 11.0 V 11.0 V 11.0 V 11.0 V 8.2 V

Features

• Floating channel designed for bootstrap operation

• Fully operational to +600 V

• Tolerant to negative transient voltage, dV/dt immune

• Gate drive supply range from 10 V to 20 V (IR2136/

IR21368), 11.5 V to 20 V (IR21362D), or 12 V to 20 V

(IR21363/IR21365/IR21366/IR21367)

• Undervoltage lockout for all channels

• Over-current shutdown turns off all six drivers

• Independent 3 half-bridge drivers

• Matched propagation delay for all channels

• Cross-conduction prevention logic

• Low side output out of phase with inputs. High side outputs

out of phase (IR213(6,63, 65, 66, 67, 68)), or in phase

(IR21362) with inputs

• 3.3 V logic compatible

• Lower di/dt gate drive for better noise immunity

• Externally programmable delay for automatic fault clear

• All parts are LEAD-FREE

IR2136/IR21362/IR21363/IR21365/

IR21366/IR21367/IR21368 (J&S) & (PbF)

28-Lead SOIC 28-Lead PDIP

44-Lead PLCC w/o 12 Leads

Data Sheet No. PD60166 revU

Feature Comparison:

IR213(6,62,63,65,66,67,68)

Typical Connection

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IR213(6,62,63,65,66,67,68)(J&S) & PbF

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are

measured under board mounted and still air conditions.

Recommended Operating Conditions

The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the

recommended conditions. All voltage parameters are absolute referenced to COM. The V

offset ratings are tested

with all supplies biased at a 15 V differential.

Symbol Definition Min Max Units

IR213(6,68) V

S1,2,3

+10 V

S1,2,3

+ 20

IR21362 V

S1,2,3

+11.5 V

S1,2,3

+ 20

B1,2,3

High side floating supply voltage

IR213(6,63,65,66,67) V

S1,2,3

+12 V

S1,2,3

+ 20

S 1,2,3

High side floating supply offset voltage Note 1 600

HO 1,2,3

High side output voltage V

S1,2,3

B1,2,3

LO1,2,3

Low side output voltage 0 V

IR213(6,68) 10 20

IR21362 11.5 20

Low side and logic fixed supply

voltage

IR213(6,63,65,66,67) 12 20

Logic ground -5 5

FLT

FAULT output voltage

RCIN

RCIN input voltage V

Note 1: Logic operational for V

of (COM - 5 V) to (COM + 600 V). Logic state held for V

of (COM - 5 V) to (COM – V

(Please refer to the Design Tip DT97-3 for more details).

Note 2: All input pins and the ITRIP and EN pins are internally clamped with a 5.2 V zener diode.

Symbol Definition Min Max Units

High side offset voltage V

B 1,2,3

- 25 V

B 1,2,3

+ 0.3

High side floating supply voltage -0.3 625

High side floating output voltage V

S1,2,3

- 0.3 V

B 1,2,3

+ 0.3

Low side and logic fixed supply voltage -0.3 25

Logic ground V

- 25 V

+ 0.3

LO1,2,3

Low side output voltage -0.3 V

+ 0.3

Input voltage LIN, HIN, ITRIP, EN V

-0.3

Lower of

+ 15) or

+ 0.3)

RCIN

RCIN input voltage V

-0.3 V

+ 0.3

FLT

FAULT output voltage

-0.3 V

+ 0.3

dV/dt

Allowable offset voltage slew rate

— 50

V/ns

(28 lead PDIP)

— 1.5

(28 lead SOIC)

— 1.6

Package power dissipation

@ T

≤ +25 °C

(44 lead PLCC)

— 2.0

(28 lead PDIP)

— 83

(28 lead SOIC)

— 78

Rth

Thermal resistance, junction to

ambient

(44 lead PLCC)

— 63

°C/W

Junction temperature — 150

Storage temperature -55 150

Lead temperature (soldering, 10 seconds) — 300

°C

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IR213(6,62,63,65,66,67,68)(J&S) & PbF

Recommended Operating Conditions - (Continued)

The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the

recommended conditions. All voltage parameters are absolute referenced to COM. The V

offset ratings are tested

with all supplies biased at a 15 V differential.

Symbol

Definition

Min Max

Units

ITRIP

ITRIP input voltage V

+ 5

Logic input voltage LIN, HIN (IR213(6,63,65,66,67,68)),

HIN (IR21362), EN

+ 5

Ambient temperature -40 125 °C

Note 2: All input pins and the ITRIP and EN pins are internally clamped with a 5.2 V zener diode.

Static Electrical Characteristics

BIAS

BS1,2,3

) = 15 V unless otherwise specified. The V

, V

, and I

parameters are referenced to V

and are

applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V

and I

parameters are referenced to COM and V

S1,2,3

and are applicable to the respective output leads: HO1,2,3 and LO1,2,3.

Symbol Definition Min Typ Max Units Test Conditions

Logic “0” input voltage LIN1,2,3, HIN1,2,3

IR213(6,63,65)

Logic “1” input voltage HIN1,2,3 IR21362

3.0

—

Logic “0” input voltage LIN1,2,3, HIN1,2,3

IR213(66,67,68)

2.5 — —

Logic “1” input Voltage LIN1,2,3, HIN1,2,3

IR213(6,63,65)

Logic “0” input voltage HIN1,2,3 IR21362

Logic “0” input voltage LIN1,2,3, HIN1,2,3

IR213(66,67,68)

—

— 0.8

EN,TH+

Enable positive going threshold — — 3

EN,TH-

Enable negative going threshold 0.8 — —

IR2136(2)(3)(6) 0.37 0.46 0.55

IT,TH+

ITRIP positive going

threshold

IR21365(7)(8) 3.85 4.30 4.75

IR2136(2)(3)(6) — 0.07 —

IT,HYS

ITRIP input hysteresis

IR21365(7)(8) — .15 —

RCIN, TH+

RCIN positive going threshold — 8 —

RCIN, HYS

RCIN input hysteresis — 3 —

High level output voltage, V

BIAS

- V

— 0.9 1.4

Low level output voltage, V

— 0.4 0.6

Io = 20 mA

IR2136(8) 8.0 8.9 9.8

IR21362 9.6 10.4 11.2

CCUV+

BSUV+

and V

supply

undervoltage positive going

threshold

IR21363(5)(6)(7) 10.6 11.1 11.6

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IR213(6,62,63,65,66,67,68)(J&S) & PbF

Static Electrical Characteristics - (Continued)

BIAS

BS1,2,3

) = 15 V unless otherwise specified. The V

, V

, and I

parameters are referenced to V

and are

applicable to all six channels (HIN1,2,3 and LIN1,2,3). The V

and I

parameters are referenced to COM and V

S1,2,3

and

are applicable to the respective output leads: HO1,2,3 and LO1,2,3.

Symbol Definition Min Typ Max Units Test Conditions

IR2136(8) 7.4 8.2 9.0

IR21362 8.6 9.4 10.2

CCUV-

BSUV-

and V

supply

undervoltage negative going

threshold

IR2136(3,5,6,7) 10.4 10.9 11.4

IR2136 0.3 0.7 —

IR21362 0.5 1.0 —

CCUVH

BSUVH

and V

supply

undervoltage lockout

hysteresis

IR2136(3,5) — 0.2 —

Offset supply leakage current — — 50

B1,2,3

= V

S1,2,3

600 V

QBS

Quiescent V

supply current — 70 120

µA

QCC

Quiescent V

supply current — 1.6 2.3 mA

= 0 V or 5 V

IN,CLAMP

Input clamp voltage (HIN, LIN, ITRIP and EN) 4.9 5.2 5.5 V I

=100 µA

IR2136(2,3,5) — 200 300

LIN+

Input bias current (LOUT = HI)

IR2136(6,7,8) — 30 100

LIN

= 5 V

IR2136(2,3,5) — 100 220

LIN-

Input bias current (LOUT = LO)

IR2136(6,7,8) — 0 1

LIN

= 0 V

IR2136(3,5) — 200 300

IR21362 — 30 100

HIN+

Input bias current (HOUT = HI)

IR2136(6,7,8) — 30 100

HIN

= 5 V

IR2136(3,5) — 100 220

HIN-

Input bias current (HOUT = LO)

IR2136(2,6,7,8) — 0 1

HIN

= 0 V

ITRIP+

“High” ITRIP input bias current — 30 100 V

ITRIP

= 5 V

ITRIP-

“Low” ITRIP input bias current — 0 1 V

ITRIP

= 0 V

EN+

“High” ENABLE input bias current — 30 100 V

ENABLE

= 5 V

EN-

“Low” ENABLE input bias current — 0 1 V

ENABLE

=0 V

RCIN

RCIN input bias current — 0 1

µA

Vrcin= 0 V or

15 V

O+

Output high short circuit pulsed current 120 200 —

Vo =0 V,

PW ≤10 µs

O-

Output low short circuit pulsed current 250 350 —

Vo =15 V,

PW ≤10 µs

on_RCIN

RCIN low on resistance — 50 100

on_FAULT

FAULT low on resistance

— 50 100

Ω

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IR213(6,62,63,65,66,67,68)(J&S) & PbF

Dynamic Electrical Characteristics

= V

BIAS

= 15 V, V

S1,2,3

= V

= COM, T

= 25 °C and CL = 1000 pF unless otherwise specified.

Symbol Definition Min Typ Max Units

Test

Conditions

IR2136(2,3,5,8) 300 425 550

Turn-on propagation delay

IR2136(6,7) — 250 —

IR2136(2,3,5,8) 250 400 550

off

Turn-off propagation delay

IR2136(6,7) — 180 —

Turn-on rise time — 125 190

Turn-off fall time — 50 75

= 0 V & 5 V

IR2136(2,3,5,8) 300 450 600

ENABLE low to output shutdown

propagation delay

IR2136(6,7) 100 250 400

IN,

= 0 V

or 5 V

ITRIP

ITRIP to output shutdown propagation delay 500 750 1000 V

ITRIP

= 5 V

ITRIP blanking time 100 150 —

FLT

ITRIP to FAULT propagation delay

400 600 800

= 0 V or 5 V

ITRIP

= 5 V

FILIN

Input filter time (HIN, LIN)

(IR213(6,62,63,65,68) only)

100 200 —

= 0 V & 5 V

FLTCLR

FAULT clear time RCIN: R = 2 MΩ, C = 1 nF 1.3 1.65 2 ms

= 0 V or 5 V

ITRIP

= 0 V

DT Deadtime 220 290 360 V

= 0 V & 5 V

MT Matching delay ON and OFF — 40 75

MDT

Matching delay, max (t

, t

off

) – min (t

, t

off

, t

off

are applicable to all 3 channels)

— 25 70

External dead

time >400 ns

PM Output pulse width matching (pwin-pwout) (Fig.2) — 40 75

Note: For high side PWM, HIN pulse width must be ≥ 1 µs.

VCC VBS ITRIP ENABLE FAULT LO1,2,3 HO1,2,3

<UVCC X X X 0 (note 1) 0 0

15 V <UVBS 0 V 5 V high imp LIN1,2,3 0

15 V 15 V 0 V 5 V high imp LIN1,2,3 HIN1,2,3

15 V 15 V >V

ITRIP

5 V 0 (note 2) 0 0

15 V 15 V 0 V 0 V high imp 0 0

Note 1: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously.

Note 2: UVCC is not latched, when V

> UV

, FAULT returns to high impedance.

Note 3: When ITRIP < V

ITRIP

, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ V

= 15 V).

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