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Abstract
For high-speed and EMC applications, it is crucial, but difficult to quantify the signal
path skew of device under test (DUT). When the device is mounted on a PCB fixture, the
PCB trace skew adds extra uncertainty to the measurement data. Attempting to de-embed
such PCB trace skew by separate test coupons just introduces even more error if the test
coupons have opposite skew. Besides showing how de-embedded results can vary,
depending on the skew of test coupons and/or fixture, this paper introduces a new
methodology, dubbed In-Fixture Skew Subtraction (IFSS) method, to quantify DUT skew
without de-embedding. A simple equation has been derived to compute both PCB and
DUT skews for those cases where the DUT has distinguishable impedance
discontinuities.
Authors Biography
Clement Luk is a Senior Signal Integrity Engineer in the High-Speed Interconnect
section at Hirose Electric USA, Inc. He is involved in high speed connector design,
device and channel simulation and measurement. He received his BSCS and MSEE from
University of Wisconsin-Madison.
Jeremy Buan is a Signal Integrity Manager in the High-Speed Interconnect section at
Hirose Electric USA, Inc. As an SI Manager, he supports the development of high-speed
connectors by both simulation and measurement. He gives SI/design assistance to
customers by providing connector models, evaluation boards, channel simulation data
and via breakout optimization. Jeremy received his BSEE and MSEE from San Jose State
University.
Tadashi Ohshida is an Engineering Manager in the High-Speed Interconnect section at
Hirose Electric USA, Inc. He joined Hirose in 2001 as a connector development engineer
for computer and telecom market. He received his BSEE from Iwate University, Iwate,
Japan.
Pin Jen Wang (Alvin) is a Signal Integrity Engineer in the High-Speed Interconnect
section at Hirose Electric USA, Inc. He is working on connector model simulation,
measurement, correlation, and development, characterization board design, and PCB
material characterization. He received his BSEE and MSEE from University of Idaho.
Yuta Oryu is a Signal Integrity Engineer at Hirose Electric USA in the High-Speed
Interconnect Department. He received his BSEE from University of Rochester.
Ching-Chao Huang, founder and president of AtaiTec Corporation, has more than 30
years of high-speed design and SI software development experience. He was advisory
engineer at IBM, R&D manager at TMA, SI manager at Rambus, and Sr. VP at Optimal.
Dr. Huang is an IEEE senior member and he pioneered In-Situ De-embedding (ISD) for
