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nRF52810 数据手册.pdf
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NRF52810是NORDIC研发的一颗低成本蓝牙5.0芯片,它出了FLASH和RAM低于NRF52832,其他参数基本上是一致的。可以替代NRF52832
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201-06-30
nRF52 2EMHFWLYHProduct SpecificationY5
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Contents
Page 2
Contents
1 Revision history................................................................................... 7
2 About this document.............................................................................................. 8
2.1 Document naming and status.................................................................................................8
2.2 Peripheral naming and abbreviations..................................................................................... 8
2.3 Register tables........................................................................................................................ 8
2.4 Registers................................................................................................................................. 9
3 Block diagram........................................................................................................10
4 Pin assignments.................................................................................................... 11
4.1 QFN48 pin assignments....................................................................................................... 11
4.2 QFN32 pin assignments....................................................................................................... 13
4.3 GPIO pins located near the radio.........................................................................................15
5 Absolute maximum ratings.................................................................................. 16
6 Recommended operating conditions.................................................................. 17
7 CPU......................................................................................................................... 18
7.1 Electrical specification...........................................................................................................18
7.2 CPU and support module configuration................................................................................18
8 Memory................................................................................................................... 20
8.1 RAM - Random access memory...........................................................................................20
8.2 Flash - Non-volatile memory.................................................................................................20
8.3 Memory map......................................................................................................................... 21
8.4 Instantiation........................................................................................................................... 21
9 AHB multilayer.......................................................................................................23
10 EasyDMA.............................................................................................................. 24
10.1 EasyDMA array list............................................................................................................. 25
11 NVMC — Non-volatile memory controller.........................................................26
11.1 Writing to flash.................................................................................................................... 26
11.2 Erasing a page in flash.......................................................................................................26
11.3 Writing to user information configuration registers (UICR)................................................. 26
11.4 Erasing user information configuration registers (UICR).................................................... 26
11.5 Erase all.............................................................................................................................. 26
11.6 Registers............................................................................................................................. 27
11.7 Electrical specification.........................................................................................................29
12 BPROT — Block protection................................................................................30
12.1 Registers............................................................................................................................. 31
13 FICR — Factory information configuration registers.......................................35
13.1 Registers............................................................................................................................. 35
14 UICR — User information configuration registers........................................... 44
14.1 Registers............................................................................................................................. 44
15 Peripheral interface............................................................................................. 58
15.1 Peripheral ID....................................................................................................................... 58
15.2 Peripherals with shared ID..................................................................................................58
15.3 Peripheral registers............................................................................................................. 59
15.4 Bit set and clear..................................................................................................................59
15.5 Tasks................................................................................................................................... 59
15.6 Events..................................................................................................................................59
15.7 Shortcuts............................................................................................................................. 59
15.8 Interrupts............................................................................................................................. 60
16 Debug....................................................................................................................61
16.1 DAP - Debug Access Port..................................................................................................61
Contents
Page 3
16.2 CTRL-AP - Control Access Port......................................................................................... 61
16.3 Debug interface mode.........................................................................................................63
16.4 Real-time debug..................................................................................................................63
17 Power and clock management...........................................................................65
17.1 Current consumption scenarios.......................................................................................... 65
18 POWER — Power supply....................................................................................67
18.1 Regulators........................................................................................................................... 67
18.2 System OFF mode..............................................................................................................68
18.3 System ON mode............................................................................................................... 68
18.4 Power supply supervisor.....................................................................................................69
18.5 RAM sections...................................................................................................................... 70
18.6 Reset................................................................................................................................... 70
18.7 Retained registers............................................................................................................... 71
18.8 Reset behavior.................................................................................................................... 71
18.9 Registers............................................................................................................................. 72
18.10 Electrical specification.......................................................................................................86
19 CLOCK — Clock control.....................................................................................87
19.1 HFCLK clock controller....................................................................................................... 87
19.2 LFCLK clock controller........................................................................................................89
19.3 Registers............................................................................................................................. 91
19.4 Electrical specification.........................................................................................................94
20 GPIO — General purpose input/output............................................................. 96
20.1 Pin configuration................................................................................................................. 96
20.2 GPIO located near the RADIO........................................................................................... 98
20.3 Registers............................................................................................................................. 98
20.4 Electrical specification.......................................................................................................139
21 GPIOTE — GPIO tasks and events..................................................................142
21.1 Pin events and tasks........................................................................................................ 142
21.2 Port event..........................................................................................................................143
21.3 Tasks and events pin configuration.................................................................................. 143
21.4 Registers........................................................................................................................... 143
21.5 Electrical specification.......................................................................................................152
22 PPI — Programmable peripheral interconnect...............................................154
22.1 Pre-programmed channels................................................................................................155
22.2 Registers........................................................................................................................... 155
23 RADIO — 2.4 GHz Radio.................................................................................. 191
23.1 EasyDMA...........................................................................................................................191
23.2 Packet configuration..........................................................................................................192
23.3 Maximum packet length.................................................................................................... 193
23.4 Address configuration........................................................................................................193
23.5 Data whitening.................................................................................................................. 193
23.6 CRC...................................................................................................................................194
23.7 Radio states...................................................................................................................... 195
23.8 Transmit sequence............................................................................................................195
23.9 Receive sequence.............................................................................................................197
23.10 Received Signal Strength Indicator (RSSI).....................................................................198
23.11 Interframe spacing...........................................................................................................198
23.12 Device address match.................................................................................................... 199
23.13 Bit counter....................................................................................................................... 199
23.14 Registers......................................................................................................................... 200
23.15 Electrical specification.....................................................................................................216
24 TIMER — Timer/counter....................................................................................220
24.1 Capture..............................................................................................................................221
24.2 Compare............................................................................................................................221
24.3 Task delays....................................................................................................................... 221
24.4 Task priority.......................................................................................................................221
24.5 Registers........................................................................................................................... 221
Contents
Page 4
24.6 Electrical specification.......................................................................................................227
25 RTC — Real-time counter.................................................................................228
25.1 Clock source..................................................................................................................... 228
25.2 Resolution versus overflow and the PRESCALER........................................................... 228
25.3 COUNTER register............................................................................................................229
25.4 Overflow features.............................................................................................................. 229
25.5 TICK event........................................................................................................................ 229
25.6 Event control feature.........................................................................................................230
25.7 Compare feature............................................................................................................... 230
25.8 TASK and EVENT jitter/delay...........................................................................................232
25.9 Reading the COUNTER register.......................................................................................234
25.10 Registers......................................................................................................................... 234
25.11 Electrical specification.....................................................................................................240
26 RNG — Random number generator................................................................ 241
26.1 Bias correction.................................................................................................................. 241
26.2 Speed................................................................................................................................ 241
26.3 Registers........................................................................................................................... 241
26.4 Electrical specification.......................................................................................................243
27 TEMP — Temperature sensor.......................................................................... 244
27.1 Registers........................................................................................................................... 244
27.2 Electrical specification.......................................................................................................249
28 ECB — AES electronic codebook mode encryption......................................250
28.1 Shared resources..............................................................................................................250
28.2 EasyDMA...........................................................................................................................250
28.3 ECB data structure............................................................................................................250
28.4 Registers........................................................................................................................... 251
28.5 Electrical specification.......................................................................................................252
29 CCM — AES CCM mode encryption................................................................253
29.1 Shared resources..............................................................................................................253
29.2 Key-steam generation....................................................................................................... 253
29.3 Encryption..........................................................................................................................254
29.4 Decryption......................................................................................................................... 254
29.5 AES CCM and RADIO concurrent operation....................................................................255
29.6 Encrypting packets on-the-fly in radio transmit mode.......................................................255
29.7 Decrypting packets on-the-fly in radio receive mode........................................................256
29.8 CCM data structure...........................................................................................................257
29.9 EasyDMA and ERROR event...........................................................................................258
29.10 Registers......................................................................................................................... 258
29.11 Electrical specification.....................................................................................................262
30 AAR — Accelerated address resolver.............................................................263
30.1 Shared resources..............................................................................................................263
30.2 EasyDMA...........................................................................................................................263
30.3 Resolving a resolvable address........................................................................................263
30.4 Use case example for chaining RADIO packet reception with address resolution using
AAR.......................................................................................................................................264
30.5 IRK data structure.............................................................................................................264
30.6 Registers........................................................................................................................... 265
30.7 Electrical specification.......................................................................................................267
31 SPIM — Serial peripheral interface master with EasyDMA............................268
31.1 Shared resources..............................................................................................................268
31.2 EasyDMA...........................................................................................................................269
31.3 SPI master transaction sequence.....................................................................................270
31.4 Low power.........................................................................................................................271
31.5 Master mode pin configuration......................................................................................... 271
31.6 Registers........................................................................................................................... 272
31.7 Electrical specification.......................................................................................................277
32 SPIS — Serial peripheral interface slave with EasyDMA...............................279
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