Altera Corporation 1
AN-469-1.1
Application Note 469
Stratix III Design Guidelines
Introduction
Stratix
®
III devices are engineered for high-speed core performance and
high-speed I/O with the best signal integrity in the industry, combined
with low-static and dynamic-power consumption. The devices also offer
increased logic density, so you can integrate more of your product to
reduce cost and board space.
It is important to follow Altera recommendations throughout the design
process for high-density, high-performance Stratix III designs. Planning
the FPGA and system early in the design process is crucial to your
success. This document provides an easy-to-use set of guidelines and a
list of factors to consider in Stratix III designs, but does not include all the
details about the product. It includes pointers to other documentation
where you can find detailed specifications, device feature descriptions,
and additional guidelines. The material covers the Stratix III device
architecture as well as aspects of the Quartus
®
II software and third-party
tools that you might use in your design.
The guidelines presented in this document will help you improve
productivity and avoid common design pitfalls. The document discusses
various stages of the design flow in the order that each stage is typically
performed, as shown in Table 1. You can use the “Design Checklist,” on
page 65 to help verify that you have followed each of the guidelines.
Table 1. Summary of Design Flow Stages and Guideline Topics (Part 1 of 2)
Stages of Design Flow Guideline Topics
“Device Selection,” on page 2
Device information, determining device density, package
offerings, speed grade, core voltage, migration, and
HardCopy
®
ASICs
“Planning for Device Configuration,” on page 6
Configuration scheme overview, configuration features,
Quartus II settings, optional pins
“Early System Planning,” on page 12
Planning: design specifications, IP selection, on-chip
debugging, early power estimation
“Board Design Considerations,” on page 18
Power-up, power pins, configuration pins, signal integrity,
board-level verification
“I/O and Clock Planning,” on page 27
Pin assignments, early pin planning, I/O features and
connections, clock and PLL selection, SSN
“Design and Compilation,” on page 42
Synthesis tools, coding styles and recommendations, planning
for hierarchical or team-based design, SOPC Builder
May 2008, version 1.1
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