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DO NOT SPECIFY OR CLAIM COMPLIANCE TO THIS
DRAFT SPECIFICATION
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PICMG
2.16 Draft 0.9.3
August 28, 2001
PICMG
2.16 Draft 0.9.3
CompactPCI
Packet Switching Backplane
DO NOT SPECIFY OR CLAIM CONFORMANCE TO THIS DRAFT SPECIFICATION
Copyright 2001, PCI Industrial Computer Manufacturers Group.
The attention of adopters is directed to the possibility that compliance with or adoption of
PICMG
specifications may require use of an invention covered by patent rights.
PICMG
shall not be responsible for identifying patents for which a license may be
required by any PICMG
specification, or for conducting legal inquiries into the legal
validity or scope of those patents that are brought to its attention. PICMG
specifications
are prospective and advisory only. Prospective users are responsible for protecting
themselves against liability for infringement of patents.
NOTICE:
The information contained in this document is subject to change without notice. The
material in this document details a PICMG
specification in accordance with the license
and notices set forth on this page. This document does not represent a commitment to
implement any portion of this specification in any company's products.
WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE
ACCURATE, PICMG
MAKES NO WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED
TO ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF
MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR
PURPOSE OR USE.
In no event shall PICMG
be liable for errors contained herein or for indirect, incidental,
special, consequential, reliance or cover damages, including loss of profits, revenue, data
or use, incurred by any user or any third party.
Compliance with this specification does not absolve manufacturers of
CompactPCI
/
Packet Switching Backplane equipment from the requirements of safety and regulatory
agencies (UL, CSA, FCC, IEC, etc.).
PICMG
, CompactPCI
, and the PICMG
and CompactPCI
logos are registered
trademarks of the PCI Industrial Computer Manufacturers Group.
All other brand or product names may be trademarks or registered trademarks of their
respective holder.
PICMG
2.16 Draft 0.9.3
CompactPCI
Packet Switching Backplane
i
DO NOT SPECIFY OR CLAIM CONFORMANCE TO THIS DRAFT SPECIFICATION
Contents
1 INTRODUCTION................................................................................................... 1
1.1 Objectives of the CompactPCI
Packet Switching Backplane.........................1
1.2 Applicable Documents......................................................................................3
1.3 Administration................................................................................................... 4
1.4 Special Word Usage.......................................................................................... 6
1.5 Name And Logo Usage.....................................................................................6
1.6 Signal Naming Conventions.............................................................................. 6
1.7 Intellectual Property .......................................................................................... 7
1.8 Acronyms .......................................................................................................... 7
1.9 Definitions......................................................................................................... 8
2 PACKET SWITCHING BACKPLANE OVERVIEW......................................... 11
2.1 Node Slot Overview........................................................................................ 12
2.2 Fabric Slot Overview ...................................................................................... 12
2.3 Link Port Overview......................................................................................... 13
2.4 Link Overview................................................................................................. 13
2.5 Hot Swap Interoperability ............................................................................... 14
3 COMPATIBILITY REQUIREMENTS ................................................................ 15
3.1 Keying Requirements...................................................................................... 15
3.1.1 Node Board Keying Requirements................................................................ 15
3.1.1.1 Alternate Node Board Keying Compliance........................................... 15
3.1.2 Fabric Board Keying ..................................................................................... 16
3.1.2.1 Standard Fabric Board Keying..............................................................16
3.1.2.2 Extended Fabric Board Keying ............................................................. 16
3.1.3 Node Slot Keying Requirements................................................................... 17
3.1.3.1 Alternate Node Slot Keying Compliance.............................................. 17
3.1.4 Standard Fabric Slot Keying .........................................................................17
3.1.5 Extended Fabric Slot Keying......................................................................... 18
3.2 Compatibility Glyph Requirements................................................................. 18
3.2.1 Backplane Glyph Requirements.................................................................... 19
3.2.2 Node Board Glyph Requirements ................................................................. 20
3.2.3 Fabric Board Glyph Requirements................................................................21
3.2.4 Glyph Designation of Slot and Board Compatibility .................................... 21
PICMG
2.16 Draft 0.9.3
ii CompactPCI
Packet Switching Backplane
DO NOT SPECIFY OR CLAIM CONFORMANCE TO THIS DRAFT SPECIFICATION
3.3 Pin Requirements ............................................................................................ 22
3.3.1 Common Node and Fabric Slot Requirements.............................................. 23
3.3.1.1 Slot Requirements for PCI_PRESENT# (P1-B6).................................23
3.3.1.2 Slot Requirements for Power and Ground ............................................ 23
3.3.1.3 Slot Requirements for PCI_RST# (P1-C5)........................................... 23
3.3.1.4 Slot Requirements for SYSEN# (P2-C2)..............................................23
3.3.1.5 Slot Requirements for PCI_CLK (P1-D6) ............................................ 23
3.3.1.6 Slot Requirements for ENUM# (P1-C25)............................................. 24
3.3.1.7 Slot Requirements for HEALTHY# (P1-B4)........................................ 24
3.3.1.8 Slot Requirements for BD_SEL# (P1-D15)..........................................24
3.3.1.9 Slot Requirements for CompactPCI Bus Signals.................................. 24
3.3.1.10 Slot Requirements for System Management Bus............................... 24
3.3.2 Node Slot Pin Requirements ......................................................................... 24
3.3.2.1 Node Slot BP(I/O) Pin Requirements ................................................... 24
3.3.2.2 Node Slot Isolation Pin Requirements .................................................. 24
3.3.2.3 Node Slot Geographic Address (GA[4:0]) (P2 Row 22) ...................... 25
3.3.3 Fabric Slot Pin Requirements........................................................................ 25
3.3.3.1 Standard Fabric Slot Link Port Pin Requirements ................................ 25
3.3.3.2 Standard Fabric Slot BP(I/O) Pin Requirements................................... 26
3.3.3.3 Standard Fabric Slot Isolation Pin Requirements.................................. 26
3.3.3.4 Extended Fabric Slot Link Port Pin Requirements ...............................26
3.3.3.5 Extended Fabric Slot BP(I/O) Pin Requirements.................................. 27
3.3.3.6 Extended Fabric Slot Isolation Pin Requirements................................. 27
3.3.3.7 Fabric Slot Geographic Address (GA[4:0]) (P2 Row 22)..................... 27
3.3.3.8 Fabric Slot Shelf Geographic Address (SGA[4:0]) (P3-Row 19)......... 28
3.3.4 Common Node and Fabric Board Pin Requirements.................................... 28
3.3.4.1 Board Requirements for PCI_PRESENT# (J1-B6)............................... 28
3.3.4.2 Board Requirements for Power and Ground......................................... 29
3.3.4.3 Board Requirements for SYSEN# (J2-C2) ........................................... 29
3.3.4.4 Board Requirements for ENUM# (J1-C25) .......................................... 29
3.3.4.5 Board Requirements for HEALTHY# (J1-B4) ..................................... 29
3.3.4.6 Board Requirements for BD_SEL# (J1-D15) ....................................... 29
3.3.4.7 Board Requirements for CompactPCI Bus Signals............................... 29
3.3.4.8 Board Requirements for PICMG 2.9 System Management Bus...........29
3.3.5 Node Board Pin Requirements...................................................................... 30
3.3.5.1 Node Board Geographic Address (GA[4:0]) (J2-Row 22) ................... 30
3.3.6 Fabric Board Pin Requirements .................................................................... 30
3.3.6.1 Fabric Board Geographic Address (GA[4:0]) (J2-Row 22).................. 30
PICMG
2.16 Draft 0.9.3
CompactPCI
Packet Switching Backplane
iii
DO NOT SPECIFY OR CLAIM CONFORMANCE TO THIS DRAFT SPECIFICATION
3.3.6.2 Fabric Board Shelf Geographic Address (SGA[4:0]) (J3-Row 19) ...... 30
3.4 Link and Link Port Requirements ................................................................... 31
3.4.1 Backplane Link and Link Port Requirements................................................33
3.4.2 Fabric Board Link and Link Port Requirements ........................................... 34
3.4.3 Node Board Link and Link Port Requirements............................................. 34
3.5 Configuration Requirements ........................................................................... 34
3.6 CompactPCI/PSB Hot Swap Requirements.................................................... 35
3.6.1 CompactPCI/PSB Hot Swap Board Requirements ....................................... 35
3.6.1.1 Common Hot Swap Board Requirements............................................. 35
3.6.1.2 Boards Without a CompactPCI Bus Interface....................................... 36
3.6.1.3 Boards With a CompactPCI Bus Interface............................................ 37
3.6.2 Hot Swap CompactPCI/Packet Switching Backplane Requirements ........... 37
3.6.2.1 Slots Without CompactPCI Bus Connections....................................... 37
3.6.2.2 Slots With CompactPCI Bus Connections............................................38
4 ELECTRICAL REQUIREMENTS....................................................................... 39
4.1 Differential Impedance Requirements............................................................. 39
4.2 PSB Backplane Electrical Requirements ........................................................39
4.3 Node and Fabric Slot Electrical Requirements ............................................... 39
4.3.1 Node and Fabric Slot PCI_PRESENT# (P1-B6)........................................... 39
4.3.2 Node and Fabric Slot SYSEN# (P2-C2) ....................................................... 40
4.3.3 Node and Fabric Slot PCI_CLK (P1-D6)...................................................... 40
4.3.4 Node and Fabric Slot PCI_RST# (P1-C5) .................................................... 40
4.3.5 Node and Fabric Slot GA[4:0] (P2-Row 22)................................................. 40
4.3.6 Node and Fabric Slot Row Z......................................................................... 40
4.3.7 Fabric Slot SGA[4:0] (P3-Row19)................................................................ 40
4.3.8 Node Slot BP(I/O) (P3-Row19) .................................................................... 40
4.4 Node and Fabric Board Electrical Requirements............................................ 40
4.4.1 Node and Fabric Board BP(I/O) Pins............................................................ 41
4.4.2 Node and Fabric Board PCI_PRESENT# (J1-B6)........................................41
4.4.3 Node and Fabric Board SYSEN# (J2-C2)..................................................... 41
4.4.4 Node and Fabric Board CompactPCI Bus Signals........................................ 41
4.4.5 Node and Fabric Board Row Z...................................................................... 42
4.4.6 Node and Fabric Board Row F......................................................................42
4.4.7 Node and Fabric Board Link Port Interface ..................................................42
4.4.8 Node and Fabric Board GA[4:0] (J2-Row 22)..............................................42
4.4.9 Fabric Board SGA[4:0] (J3-Row19)............................................................. 42
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