24LC01B02B资源-CSDN文库

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

1997 Microchip Technology Inc. DS21222A-page 1

24LC01B/02B MODULES

FEATURES

• ISO 7816 Compliant pad locations

• Low power CMOS technology

- 1 mA active current typical

- 10

A standby current typical at 5.5V

• Organized as a single block of 128 bytes (128 x 8)

or 256 bytes (256 x 8)

• 2-wire serial interface bus, I

C™ compatible

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical write cycle time for page-write

• ESD protection > 4 kV

• 1,000,000 E/W cycles guaranteed

• Data retention > 200 years

• Temperature ranges available:

DESCRIPTION

The Microchip Technology Inc. 24LC01B and 24LC02B

are 1K-bit and 2K-bit Electrically Erasable PROMs in

ISO modules for smart card applications. The devices

are organized as a single block of 128 x 8-bit or 256 x

8-bit memory with a two-wire serial interface. The

24LC01B and 24LC02B also have page-write capabil-

ity for up to 8 bytes of data.

ISO MODULE LAYOUT

BLOCK DIAGRAM

- Commercial (C): 0

C to +70

VSS

SDA

SCL

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA SCL

VCC

VSS

1K/2K I

™

Serial EEPROMs in ISO Micromodules

24LC01B/02B Modules

DS21222A-page 2



1997 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

................-0.6V to V

+1.0V

Storage temperature ..................................... -65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

ESD protection on all pads.............................................

≥

4 kV

*Notice:

Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1: PAD FUNCTION TABLE

1.2 P

ad Descriptions

1.2.1 SDA (Serial Data)

This is a bi-directional pad used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to V

(typical 10 K

Ω

for 100 kHz, 2 K

Ω

for

400 kHz).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are reserved

for indicating the START and STOP conditions.

1.2.2 SCL (Serial Clock)

This input is used to synchronize the data transfer from

and to the device.

Name Function

SDA

SCL

Ground

Serial Address/Data I/O

Serial Clock

+2.5V to 5.5V Power Supply

TABLE 1-1 DC CHARACTERISTICS

All Parameters apply across the recom-

mended operating ranges unless other-

wise noted.

Commercial (C): Tamb = 0˚C to +70˚C, V

= 2.5V to 5.5V

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:

High level input voltage V

0.7 V

V (Note)

Low level input voltage V

0.3 V

V (Note)

Hysteresis of Schmitt trigger inputs V

HYS

0.05 V

— V Vcc

≥

2.5V (Note)

Low level output voltage V

0.40 V I

= 3.0 mA, V

= 4.5V

= 2.1 mA, V

= 2.5V

Input leakage current I

-10 10

A V

= V

or V

Output leakage current I

-10 10

A V

OUT

= V

or V

Pin capacitance (all inputs/outputs) C

OUT

— 10 pF V

= 5.0V (Note)

Tamb = 25˚C, f = 1 MHz

Operating current I

Write — 3 mA V

= 5.5V, SCL = 400 kHz

Read — 1 mA V

= 5.5V, SCL = 400 kHz

Standby current I

CCS

— 100

A V

= 5.5V, SDA = SCL = V

Note:

This parameter is periodically sampled and not 100% tested.

24LC01B/02B Modules



1997 Microchip Technology Inc. DS21222A-page 3

TABLE 1-2 AC CHARACTERISTICS

FIGURE 1-1: BUS TIMING DATA

All parameters apply across the speciﬁed operat-

ing ranges unless otherwise noted.

Vcc = 2.5V to 5.5V

Commercial (C): Tamb = 0

C to +70

Parameter Symbol

Vcc = 2.5V - 5.5V

STD MODE

Vcc = 4.5V - 5.5V

FAST MODE

Units Remarks

Min. Max. Min. Max.

Clock frequency F

CLK

— 100 — 400 kHz

Clock high time T

HIGH

4000 — 600 — ns

Clock low time T

LOW

4700 — 1300 — ns

SDA and SCL rise time T

— 1000 — 300 ns (Note 1)

SDA and SCL fall time T

— 300 — 300 ns (Note 1)

START condition hold time T

STA

4000 — 600 — ns After this period the ﬁrst

clock pulse is generated

START condition setup time T

STA

4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

DAT

0 — 0 — ns (Note 2)

Data input setup time T

DAT

250 — 100 — ns

STOP condition setup time T

STO

4000 — 600 — ns

Output valid from clock T

— 3500 — 900 ns (Note 2)

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free

before a new transmission

can start

Output fall time from V

minimum to V

maximum

— 250 20 +0.1

250 ns (Note 1), C

≤

100 pF

Input ﬁlter spike suppression

(SDA and SCL pins)

— 50 — 50 ns (Notes 1, 3)

Write cycle time T

— 10 — 10 ms Byte or Page mode

Endurance 1M — 1M — cycles 25

C, V

= 5.0V, Block

Mode (Note 4)

Note 1:

Not 100% tested. C

= total capacitance of one bus line in pF.

As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

The combined T

and V

HYS

speciﬁcations are due to Schmitt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI speciﬁcation for standard operation.

This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc

application, please consult the Total Endurance Model which can be obtained on our BBS or website.

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