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TDA18271 DATASHEET
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飞利浦公司旗下的恩智浦生产PC电视硅天线TDA18271的说明书
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1. General description
The TDA18271HD is a Silicon Tuner IC designed mainly for terrestrial analog and digital
TV reception. The TDA18271HD integrates the overall tuning function, including
selectivity.
The TDA18271HD is compatible with all analog and digital TV standards and delivers a
low IF signal to a demodulator (for analog TV) and/or channel decoder (for digital TV).
This specification is based on software version 3.4.
2. Features
n Fully integrated RF tracking filters for unwanted signal suppression
n Fully integrated IF selectivity (no need for external SAW filters)
n Worldwide multistandard terrestrial (all analog and digital worldwide terrestrial
standards supported)
n Integrated loop-through and slave tuner output for straightforward multi-silicon tuner
application
n Fully integrated oscillators with no external components
n Alignment free
n Integrated wide-band gain control
n Single 3.3 V power supply
n Low power consumption
n Crystal oscillator output buffer (16 MHz) for single crystal applications
n I
2
C-bus interface compatible with 3.3 V and 5 V microcontrollers
n Three Standby modes
n RoHS packaging
3. Applications
3.1 Target applications
n Hybrid (analog and digital TV) for PCTV, DVD-R and TV applications
n Application optimization is described in application notes
AN602
,
AN604
and
AN605
TDA18271HD
Silicon Tuner IC
Rev. 03 — 11 September 2008 Product data sheet
TDA18271HD_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 11 September 2008 2 of 69
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
3.2 Key benefits
n The TDA18271HD is a Silicon Tuner targeting digital and analog TV applications. The
aim is to match the performance of conventional Can tuners while reducing the size of
the tuner function. Additionally, the following benefits are provided:
u Easy on-board integration
u Easy dual tuner configuration
u Drastic size reduction of the tuner function and power consumption
4. Quick reference data
[1] Measured with TDA10048HN channel decoder.
[2] Measured with TDA8295 IF modulator.
5. Ordering information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
f
RF(STO)
RF frequency on pin
STO
slave tuner output 45 - 864 MHz
NF
tun
tuner noise figure maximum gain - 5.5 - dB
ϕ
n
phase noise 1 kHz and 10 kHz - −89 - dBc/Hz
P power dissipation - 780 - mW
V
i(max)
maximum input voltage 1 dB gain compression,
one analog TV signal at
RF input (−5 dBm)
- 103 - dBµV
α
image
image rejection - 65 - dB
S
dig
digital sensitivity DVB-T (64 QAM
2
⁄
3
);
BER = 2.10
−4
[1]
- −82 - dBm
S
a
analog sensitivity 50 dB video SNR
weighted 22 dBµV
(color loss)
[2]
-58-dBµV
Table 2. Ordering information
Type number Package
Name Description Version
TDA18271HD/C2 HLQFN64R plastic thermal enhanced low profile quad flat
package; no leads; 64 terminals; resin based;
body 9 × 9 × 1.6 mm
SOT903-1
TDA18271HD_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 11 September 2008 3 of 69
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
6. Block diagram
Fig 1. Block diagram
001aag453
AGC CONTROL
ATTENUATORS
TDA18271HD
TEST SIGNAL
GENERATOR
CALIBRATION
SYNTHESIZER
MAIN
SYNTHESIZER
DUAL TUNER
PROTOCOL
DIVIDER
crystal
oscillator
DC-to-DC
CONVERTER
DIGITAL
CIRCUITRY
LC
tracking
filters
RF
polyphase
filter
IF
polyphase
filter
IF
low-pass
filter
VT_CAL CP_CAL
XTALP
CP_LO
XTALN VT_FINE
VT_COARSE
RF
AGC
IF
AGC
IFOUTN
IFOUTP
V_IFAGC
45
FREEZE
28
MASTERSYNC
19
46
47
AGC
VCO
LNA
AGC1
AGC2
RF_IN
10
13
15
CONTROL
INTERFACE
SCLAS SDA
38
32 39 35 34 26 2227 24 21
LT
8
FM_IN
STO
mixer
TDA18271HD_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 11 September 2008 4 of 69
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 2. Pin configuration
TDA18271HD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
V_IFAGC
IFOUTP
IFOUTN
VCC
GND
CAPREG28
GND
CAPREG18
SDA
SCL
GND
GND
VT_CAL
CP_CAL
VCC
GND
GND
GND
GND
GND
GND
GND
FM_IN
VCC
RF_IN
GND
CAPRFAGC
LT
GND
STO
VCC
CAPREGVCO
VCC
MASTERSYNC
CAPFILTVCO
VT_COARSE
VT_FINE
GND
CP_LO
GND
XTALP
XTALN
FREEZE
XTOUT_MS
XTOUTP
XTOUTN
AS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CAPREGFILTRF
VSYNC
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Transparent top view
terminal 1
index area
001aag454
Table 3. Pin description
Symbol Pin Description
GND 1 to 7 ground
FM_IN 8 unbalanced FM input
VCC 9 3.3 V supply voltage
RF_IN 10 unbalanced RF (TV) input
GND 11 ground
CAPRFAGC 12 RF AGC filtering
TDA18271HD_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 11 September 2008 5 of 69
NXP Semiconductors
TDA18271HD
Silicon Tuner IC
LT 13 loop-through output
GND 14 ground
STO 15 slave tuner output
VCC 16 3.3 V supply voltage
CAPREGVCO 17 VCO supply decoupling
VCC 18 3.3 V supply voltage
MASTERSYNC 19 synchronization signal for dual tuner applications; leave open for
single tuner applications
CAPFILTVCO 20 VCO reference decoupling
VT_COARSE 21 LO tuning voltage input
VT_FINE 22 LO tuning voltage input
GND 23 ground
CP_LO 24 charge pump of the local synthesizer
GND 25 ground
XTALP 26 crystal oscillator input
XTALN 27 crystal oscillator input
FREEZE 28 synchronization signal for multi tuner applications; leave open
for single tuner applications
XTOUT_MS 29 XTOUT mode and master/slave selection
XTOUTP 30 crystal oscillator output buffer
XTOUTN 31 crystal oscillator output buffer
AS 32 I
2
C-bus address selection input
VCC 33 3.3 V supply voltage
CP_CAL 34 charge pump of the calibration synthesizer
VT_CAL 35 tuning voltage of the calibration synthesizer
GND 36, 37 ground
SCL 38 I
2
C-bus clock input
SDA 39 I
2
C-bus data input/output
CAPREG18 40 internal regulator decoupling
GND 41 ground
CAPREG28 42 internal regulator decoupling
GND 43 ground
VCC 44 3.3 V supply voltage
IFOUTN 45 IF output
IFOUTP 46 IF output
V_IFAGC 47 IF gain control input
GND 48 to 50 ground
VSYNC 51 vertical synchronization input for analog applications; connect to
ground for digital applications
CAPREGFILTRF 52 internal regulator decoupling
GND 53 to 64 ground
GND exposed die ground
Table 3. Pin description
…continued
Symbol Pin Description
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