# Fully-Pipelined-Edge-Detector-Algorithms-Using-VHDL
Roberts, Prewitt, Scharr, and Sobel edge detector algorithms <br/>
The core includes Roberts, Prewitt, Scharr, and Sobel edge detector algorithms. The design is fully pipelined. The latency is 5. After 5 clocks, it produces output at each clock. The desisn is generic as well. You can use the edge detector in the top module. Only the hardware of edge detector algorithm you choose is generated. <br/>
My design is published at opencores.org as well. <br/>
https://opencores.org/projects/fully-pipelined-edge-detection-algorithms <br/>
You can reach me via Linkedin <br/>
https://www.linkedin.com/in/muhammed-kocao%C4%9Flu-2b661b178/ <br/>
# Sobel <br/>
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# Prewitt <br/>
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# Scharr <br/>
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# Robets <br/>
全流水线边缘检测器算法使用 VHDL源码
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2023-01-15
09:04:49
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01Fully-Pipelined-Edge-Detector-Algorithms-Using-VHDL-main.zip （21个子文件） 
Fully-Pipelined-Edge-Detector-Algorithms-Using-VHDL-main src 
PrewittFilter.vhd 6KB ScharrFilter.vhd 6KB RobertsFilter.vhd 5KB EdgeDetection_pkg.vhd 485B SobelFilter.vhd 6KB tb_EdgeDetection.vhd 946B OperatorOverloading_pkg.vhd 3KB EdgeDetection.vhd 4KB test bench 
venice_filtered_vect_hex.txt 2.92MB raw_scharr.txt 1.75MB raw_prewitt_roberts_sobel.txt 2.33MB filtered_sobel.txt 2.92MB filtered_prewitt.txt 2.92MB tb_EdgeDetection.vhd 5KB filtered_roberts.txt 2.92MB filtered_scharr.txt 2.92MB results 
sobel.jpg 77KB roberts.jpg 46KB scharr.jpg 113KB prewitt.jpg 67KB README.md 1KB资源评论
