2011年IEEE JSSC论文（6月）
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2011-09-29
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2011年6月.rar （19个子文件） 
6月 
A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN WiMAX Receivers.pdf 1.57MB 7.4 Gb s 6.8 mW Source Synchronous Receiver in 65 nm CMOS.pdf 3.06MB A Wideband Millimeter-Wave Frequency Synthesis Architecture Using Multi-Order Harmonic-Synthesis and Variable $N$-Push Frequency Multiplication.pdf 3.32MB A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches.pdf 3.2MB A Supply-Rail-Coupled eTextiles Transceiver for Body-Area Networks.pdf 1.87MB A 10.2 Mbps Pulse Harmonic Modulation Based Transceiver for Implantable Medical Devices.pdf 2.29MB A 3.6 $mu$ s Latency Asynchronous Frame-Free Event-Driven Dynamic-Vision-Sensor.pdf 3.87MB A 10-MHz Green-Mode Automatic Reconfigurable Switching Converter for DVS-Enabled VLSI Systems.pdf 3.5MB A Micropower Low-Noise Neural Recording Front-End Circuit for Epileptic Seizure Detection.pdf 3.42MB An 847–955 Mb s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $mu$m CMOS.pdf 4.01MB A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver.pdf 3.05MB A 100 pJ bit, (32,8) CMOS Analog Low-Density Parity-Check Decoder Based on Margin Propagation.pdf 2.1MB Analysis and Design of D-Band Injection-Locked Frequency Dividers.pdf 3.77MB A 60 pW g$_{m}$C Continuous Wavelet Transform Circuit for Portable EEG Systems.pdf 1.77MB A 10-bit, 40-MS s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit cycle Conversion Technique.pdf 1.63MB An Energy Efficient $V_{rm PP}$ Generator With Fast Ramp-Up Time for Mobile DRAM.pdf 1.99MB 1.pdf 1.9MB 1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD.pdf 2.32MB A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver.pdf 2.3MB资源评论
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