A Whitepaper on SRAM FPGA security
Written by Ray Schouten
x1.2
1.0 Introduction
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be
programmed from an external source. This procedure allows anyone to easily monitor
the bit-stream, and clone the device. The problem then becomes how can you effectively
protect your intellectual property from others in an architecture where the part is
externally programmed?
Implementing a microprocessor to configure the device does not address this security
issue. The microprocessor must still write the configuration data externally. The
configuration data is of finite length and can therefore be captured and used to
configure another FPGA.
Most FPGA vendors do not publish the definition of the bit-stream. It is therefore very
difficult to reverse engineer a design from a configuration bit-stream.
A FPGA bit-stream cannot be encrypted externally, because there is no way to decrypt
the data before it programs the SRAM elements. However, you can program the FPGA
and require an external device to write a random number that will enable the operation
of the FPGA. Without the proper access code, the FPGA is programmed, but disabled
and non-functional.
2.0 References
1. B. Shneier, “Applied Cryptography 2
nd
edition”, Wiley ISBN 0-471-11709-9
3.0 Scope
The method discussed in this document exploits the fact that it is difficult to reverse
engineer a design from the configuration bit-stream. This method also requires a
simple secure programmable device such as an E
2
PROM PLD or embedded
microcontroller with security bits.
This method uses a pseudo-random sequence generator in both the secure device and
the FPGA. Upon powerup, the FPGA gets programmed externally. After the FPGA is
programmed, it is disabled and non-functional. The secure device detects that the
FPGA has been programmed successfully and begins to communicate with the FPGA.
Using pseudo-random-sequence generators, the logic passes data to the FPGA. The
outputs of both sequence generators are compared in the FPGA, and the FPGA is
enabled if the sequences compare.
It is important that the pseudo-random sequence satisfy the following two requirements:
1. It must be of sufficient length to make capturing the entire sequence impractical.
Download from: www.fpga.com.cn & www.pld.com.cn
