Mobile SDR SDRAM
Mobile SDR SDRAM
Device Operations
& Timing Diagram
DEVICE OPERATIONS
2
Mobile SDR SDRAM
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
This Mobile SDR SDRAM is organized as four independent
banks of 1,048,576 words x 16 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS
and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
: In case x 32
This Mobile SDR SDRAM is organized as four independent
banks of 524,288 words x 32 bits memory arrays. The BA0 ~ BA1
inputs are latched at the time of assertion of RAS
and CAS to
select the bank to be used for the operation. The bank addresses
BA0 ~ BA1 are latched at bank active, read, write, mode register
set and precharge operations.
ADDRESS INPUTS (A0 ~ A11)
: In case x 16
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
are latched along with CAS
, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0 ~ A10).
The 11 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
are latched along with CAS
, WE and BA0 ~ BA1 during read or
write command.
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
This Mobile SDR SDRAM is organized as four independent
banks of 2,097,152 words x 16 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS
and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
: In case x 32
This Mobile SDR SDRAM is organized as four independent
banks of 1,048,576 words x 32 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS
and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A11)
: In case x 16
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS
, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
are latched along with CAS
, WE and BA0 ~ BA1 during read or
write command.
A. DEVICE OPERATIONS
ADDRESSES of 64Mb ADDRESSES of 128Mb
DEVICE OPERATIONS
3
Mobile SDR SDRAM
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16
This Mobile SDR SDRAM is organized as four independent
banks of 4,194,304 words x 16 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS
and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
: In case x 32
This Mobile SDR SDRAM is organized as four independent
banks of 2,097,152 words x 32 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS
and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 16
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS
, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A0 ~ A11).
The 12 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS
, WE and BA0 ~ BA1 during read or
write command.
BANK ADDRESSES (BA0 ~ BA1)
: In case x 16 1/CS
This Mobile SDR SDRAM is organized as four independent
banks of 8,388,608 words x 16 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS
and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
: In case x 16 2/CS
This Mobile SDR SDRAM is organized as two chips which have
four independent banks of 4,194,304 words x 16 bits memory
arrays. The BA0 ~ BA1 inputs are latched at the time of assertion
of RAS
and CAS to select the bank to be used for the operation.
The bank addresses BA0 ~ BA1 are latched at bank active, read,
write, mode register set and precharge operations.
: In case x 32
This Mobile SDR SDRAM is organized as four independent
banks of
4,194,304 words x 32 bits memory arrays. The BA0 ~
BA1 inputs are latched at the time of assertion of RAS
and CAS
to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 16 1/CS
The 23 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 10 bit column
addresses are latched along with CAS
, WE and BA0 ~ BA1 dur-
ing read or write command.
: In case x 16 2/CS
The 22 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS
, WE and BA0 ~ BA1 during read or
write command.
: In case x 32
The 22 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS
and BA0 ~
BA1 during bank activate command. The 9 bit column addresses
are latched along with CAS
, WE and BA0 ~ BA1 during read or
write command.
ADDRESSES of 256Mb ADDRESSES of 512Mb
A. DEVICE OPERATIONS (continued)
DEVICE OPERATIONS
4
Mobile SDR SDRAM
CLOCK (CLK)
The clock input is used as the reference for all Mobile SDR
SDRAM operations. All operations are synchronized to the posi-
tive going edge of the clock. The clock transitions must be mono-
tonic between V
IL
and V
IH
. During operation with CKE high all
inputs are assumed to be in a valid state (low or high) for the
duration of set-up and hold time around positive edge of the
clock in order to function well and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto Mobile SDR
SDRAM. If CKE goes low synchronously with clock (set-up and
hold time are the same as other inputs), the internal clock is sus-
pended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes low.
When all banks are in the idle state and CKE goes low synchro-
nously with clock, the Mobile SDR SDRAM enters the power
down mode from the next clock cycle. The Mobile SDR SDRAM
remains in the power down mode ignoring the other inputs as
long as CKE remains low. The power down exit is synchronous
as the internal clock is suspended. When CKE goes high at least
"1CLK + tSS" before the high going edge of the clock, then the
Mobile SDR SDRAM becomes active from the same clock edge
accepting all the input commands.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the Mobile SDR SDRAM per-
forms no operation (NOP). NOP does not initiate any new opera-
tion, but is needed to complete operations which require more
than single clock cycle like bank activate, burst read, auto
refresh, etc. The device deselect is also a NOP and is entered by
asserting CS
high. CS high disables the command decoder so
that RAS
, CAS, WE and all the address inputs are ignored.
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE
during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the Mobile SDR SDRAM. Due to asynchro-
nous nature of the internal write, the DQM operation is critical to
avoid unwanted or incomplete writes when the complete burst
write is not required. Please refer to DQM timing diagram also.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of Mobile SDR SDRAM. It programs the CAS
latency, burst type, burst length, test mode and various vendor
specific options to make Mobile SDR SDRAM useful for variety
of different applications. The default value of the mode register is
not defined, therefore the mode register must be written after
power up to operate the Mobile SDR SDRAM. The mode regis-
ter is written by asserting low on CS
, RAS, CAS and WE (The
Mobile SDR SDRAM should be in active mode with CKE already
high prior to writing the mode register). The state of address pins
A0 ~ An and BA0 ~ BA1 in the same cycle as CS
, RAS, CAS and
WE
going low is the data written in the mode register. Two clock
cycles is required to complete the write in the mode register. The
mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as
all banks are in the idle state. The mode register is divided into
various fields depending on the fields of functions. The burst
length field uses A0 ~ A2, burst type uses A3, CAS latency (read
latency from column address) use A4 ~ A6, vendor specific
options or test mode use A7 ~ A8, A10/AP ~ An and BA0 ~ BA1.
The write burst length is programmed using A9. A7 ~ A8, A10/AP
~ An and BA0 ~ BA1 must be set to low for normal Mobile SDR
SDRAM operation. Refer to the table for specific codes for vari-
ous burst length, burst type and CAS latencies.
A. DEVICE OPERATIONS (continued)
DEVICE OPERATIONS
5
Mobile SDR SDRAM
EXTENDED MODE REGISTER SET (EMRS)
1. For Internal TCSR, PASR and DS support
The extended mode register stores the data for selecting driver
strength and partial self refresh. EMRS cycle is not mandatory
and the EMRS command needs to be issued only when DS or
PASR is used. The default state without EMRS command issued
is half driver strength(for VDD 1.8V) / full driver strength(for VDD
2.5V, 3.0V) and all 4banks(full array) refreshed. The extended
mode register is written by asserting low on CS
, RAS, CAS, WE
and high on BA1, low on BA0(The Mobile SDR SDRAM should
be in all bank precharge with CKE already high prior to writing
into the extended mode register). The state of address pins A0 ~
An in the same cycle as CS
, RAS, CAS and WE going low is writ-
ten in the extended mode register. Two clock cycles are required
to complete the write operation in the extended mode register.
The mode register contents can be changed using the same
command and clock cycle requirements during operation as long
as all banks are in the idle state. A0 - A2 are used for partial self
refresh, A5 - A6 are used for Driver strength, "Low" on BA0 and
"High" on BA1 are used for EMRS. All the other address pins
except A0~A2, A5~A6, BA1, BA0 must be set to low for proper
EMRS operation. Refer to the table for specific codes.
2. For Internal TCSR, PASR support
The extended mode register stores the data for selecting partial
self refresh. EMRS cycle is not mandatory and the EMRS
command needs to be issued only when PASR is used. The
default state without EMRS command issued is all 4banks(full
array) refreshed. The extended mode register is written by
asserting low on CS
, RAS, CAS, WE and high on BA1, low on
BA0(The Mobile SDR SDRAM should be in all bank precharge
with CKE already high prior to writing into the extended mode
register). The state of address pins A0 ~ An in the same cycle as
CS
, RAS, CAS and WE going low is written in the extended
mode register. Two clock cycles are required to complete the
write operation in the extended mode register. The mode register
contents can be changed using the same command and clock
cycle requirements during operation as long as all banks are in
the idle state. A0 - A2 are used for partial self refresh, "Low" on
BA0 and "High" on BA1 are used for EMRS. All the other
address pins except A0~A2, BA1, BA0 must be set to low for
proper EMRS operation. Refer to the table for specific codes.
BANK ACTIVATE.
The bank activate command is used to select a random row in an
idle bank. By asserting low on RAS
and CS with desired row and
bank address, a row access is initiated. The read or write opera-
tion can occur after a time delay of t
RCD
(min) from the time of
bank activation. t
RCD
is an internal timing parameter of Mobile
SDR SDRAM, therefore it is dependent on operating clock fre-
quency. The minimum number of clock cycles required between
bank activate and read or write command should be calculated
by dividing t
RCD
(min) with cycle time of the clock and then round-
ing off the result to the next higher integer.
The Mobile SDR SDRAM has four internal banks in the same
chip and shares part of the internal circuitry to reduce chip area,
therefore it restricts the activation of four banks simultaneously.
Also the noise generated during sensing of each bank of Mobile
SDR SDRAM is high, requiring some time for power supplies to
recover before another bank can be sensed reliably. t
RRD
(min)
specifies the minimum time required between activating different
bank. The number of clock cycles required between different
bank activation must be calculated similar to t
RCD
specification.
The minimum time required for the bank to be active to initiate
sensing and restoring the complete row of dynamic cells is deter-
mined by t
RAS
(min). Every Mobile SDR SDRAM bank activate
command must satisfy t
RAS
(min) specification before a precharge
command to that active bank can be asserted. The maximum
time any bank can be in the active state is determined by
t
RAS
(max). The number of cycles for both t
RAS
(min) and
t
RAS
(max) can be calculated similar to t
RCD
specification.
Any system or application incorporating random access memory
products should be properly designed, tested and qulifided to
ensure proper use or access of such memory products. Dispro-
portionate, excessive and/or repeated access to a particular
address or addresses may result in reduction of product life.
A. DEVICE OPERATIONS (continued)
