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ARM966E-S技术参考手册
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ARM966E-S技术参考手册(英文版)
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Copyright © 2000, 2002, 2004 ARM Limited. All rights reserved.
ARM DDI 0213E
ARM966E-S
™
Revision: r2p1
Technical Reference Manual
ii Copyright © 2000, 2002, 2004 ARM Limited. All rights reserved. ARM DDI 0213E
ARM966E-S
Technical Reference Manual
Copyright © 2000, 2002, 2004 ARM Limited. All rights reserved.
Release Information
Proprietary Notice
Words and logos marked with
®
or
™
are registered trademarks or trademarks of ARM Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM Limited in good faith.
However, all warranties implied or expressed, including but not limited to implied warranties of
merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Confidentiality Status
This document is Open Access. This document has no restriction on distribution.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Change
July 2000 A First release
January 2002 B Second release
February 2002 C Third release
February 2002 D Fourth release
February 2004 E Fifth release r2p1
ARM DDI 0213E Copyright © 2000, 2002, 2004 ARM Limited. All rights reserved. iii
Contents
ARM966E-S Technical Reference Manual
Preface
About this manual ......................................................................................... xii
Feedback .................................................................................................... xvii
Chapter 1 Introduction
1.1 About the ARM966E-S processor ............................................................... 1-2
1.2 Silicon revision information ......................................................................... 1-5
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 About the ARM9E-S programmer’s model .................................................. 2-3
2.3 CP15 registers ............................................................................................ 2-5
Chapter 3 Memory Map
3.1 About the ARM966E-S memory map .......................................................... 3-2
3.2 Tightly-coupled memory address space ..................................................... 3-3
3.3 Bufferable write address space ................................................................... 3-4
Chapter 4 Tightly-Coupled Memory Interface
4.1 About the TCM interface ............................................................................. 4-2
4.2 TCM size ..................................................................................................... 4-3
4.3 Enabling TCM ............................................................................................. 4-4
Contents
iv Copyright © 2000, 2002, 2004 ARM Limited. All rights reserved. ARM DDI 0213E
4.4 TCM write buffers ....................................................................................... 4-7
4.5 TCM error detection signals ....................................................................... 4-8
4.6 TCMSEQ signals ........................................................................................ 4-9
4.7 Interface operation .................................................................................... 4-10
4.8 TCM implementation examples ................................................................ 4-15
Chapter 5 Bus Interface Unit
5.1 About the BIU ............................................................................................. 5-2
5.2 AHB instruction prefetch buffer ................................................................... 5-3
5.3 AHB write buffer ......................................................................................... 5-6
5.4 AHB bus master interface ........................................................................... 5-9
5.5 AHB transfer descriptions ......................................................................... 5-10
5.6 AHB clocking ............................................................................................ 5-15
5.7 CLK-to-HCLK skew .................................................................................. 5-17
Chapter 6 Coprocessor Interface
6.1 About the coprocessor interface ................................................................. 6-2
6.2 Coprocessor interface signals .................................................................... 6-3
6.3 LDC/STC .................................................................................................. 6-10
6.4 MCR/MRC ................................................................................................ 6-12
6.5 Interlocked MCR ....................................................................................... 6-13
6.6 CDP .......................................................................................................... 6-14
6.7 Privileged instructions ............................................................................... 6-15
6.8 Busy-waiting and interrupts ...................................................................... 6-16
Chapter 7 Debug Support
7.1 About the debug interface .......................................................................... 7-2
7.2 Debug systems ........................................................................................... 7-4
7.3 ARM966E-S scan chain 15 ........................................................................ 7-7
7.4 Debug interface signals .............................................................................. 7-9
7.5 ARM9E-S core clock domains .................................................................. 7-14
7.6 Determining the core and system state .................................................... 7-15
7.7 About the EmbeddedICE-RT .................................................................... 7-16
7.8 Disabling EmbeddedICE-RT .................................................................... 7-18
7.9 The debug communications channel ........................................................ 7-19
7.10 Monitor mode debug ................................................................................. 7-23
7.11 Debug additional reading .......................................................................... 7-25
Chapter 8 Embedded Trace Macrocell Interface
8.1 About the ETM interface ............................................................................. 8-2
8.2 Enabling the ETM interface ........................................................................ 8-3
8.3 ARM966E-S trace support features ............................................................ 8-4
Chapter 9 Test Support
9.1 About the ARM966E-S test methodology ................................................... 9-2
9.2 Scan insertion and ATPG ........................................................................... 9-3
Contents
ARM DDI 0213E Copyright © 2000, 2002, 2004 ARM Limited. All rights reserved. v
9.3 BIST of tightly-coupled memory .................................................................. 9-4
Appendix A Signal Descriptions
A.1 Signal properties and requirements ............................................................ A-2
A.2 Clock interface signals ................................................................................ A-3
A.3 AHB signals ................................................................................................ A-4
A.4 TCM interface signals ................................................................................. A-6
A.5 Coprocessor interface signals ................................................................... A-10
A.6 Debug signals ........................................................................................... A-12
A.7 Miscellaneous signals ............................................................................... A-14
A.8 ETM interface signals ............................................................................... A-15
A.9 Test wrapper signals ................................................................................. A-17
Appendix B AC Parameters
B.1 Timing diagrams and timing parameters ..................................................... B-2
Glossary
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资源评论
- lingdianhao2014-08-14很详细的手册。
- 小工匠0072019-09-27很棒的参考文档!
- bobby_yang_20102016-08-16不错,谢谢分享!
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