VCS仿真vivado脚本文件_vcsxpm资源-CSDN文库

共308个文件

v：81个

db：63个

sdb：43个

Vivado

FPGA

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VCS仿真vivado脚本文件（308个子文件）

.cxl.vcs_mx.lin64.cmd 3KB

.cxl.verilog.unisim.unisims_ver.lin64.cmd 958B

.cxl.vhdl.unisim.unisim.lin64.cmd 782B

.cxl.verilog.simprim.simprims_ver.lin64.cmd 530B

.cxl.verilog.xilinx_vip.xilinx_vip.lin64.cmd 306B

.cxl.verilog.unimacro.unimacro_ver.lin64.cmd 239B

.cxl.verilog.unifast.unifast_ver.lin64.cmd 235B

.cxl.verilog.secureip.secureip.lin64.cmd 227B

.cxl.vhdl.unimacro.unimacro.lin64.cmd 219B

.cxl.vhdl.unifast.unifast.lin64.cmd 215B

.cxl.verilog.xpm.xpm.lin64.cmd 212B

.cxl.vhdl.xpm.xpm.lin64.cmd 199B

.cxl.verilog.unisim.unisims_ver.lin64.cmf 84KB

.cxl.vhdl.unisim.unisim.lin64.cmf 79KB

.cxl.verilog.simprim.simprims_ver.lin64.cmf 25KB

.cxl.verilog.secureip.secureip.lin64.cmf 1KB

.cxl.vhdl.unimacro.unimacro.lin64.cmf 917B

.cxl.vhdl.secureip_vhdl_unisim.unisim.lin64.cmf 891B

.cxl.verilog.unimacro.unimacro_ver.lin64.cmf 859B

.cxl.systemverilog.xilinx_vip.xilinx_vip.lin64.cmf 603B

.cxl.systemverilog.unisim.unisims_ver.lin64.cmf 513B

.cxl.systemverilog.simprim.simprims_ver.lin64.cmf 513B

.cxl.verilog.xpm.xpm.lin64.cmf 272B

.cxl.vhdl.unifast.unifast.lin64.cmf 221B

.cxl.verilog.unifast.unifast_ver.lin64.cmf 194B

.cxl.vhdl.xpm.xpm.lin64.cmf 54B

str.db 406KB

str.db 385KB

str.db 187KB

modfilename.db 76KB

modfilename.db 68KB

str.db 35KB

str.db 32KB

modfilename.db 21KB

str.index.db 17KB

str.index.db 16KB

str.db 16KB

str.index.db 9KB

str.db 8KB

str.db 6KB

modfilename.db 2KB

compat.db 1KB

str.index.db 1KB

str.index.db 874B

modfilename.db 814B

modfilename.db 672B

modfilename.db 657B

str.index.db 480B

dumpcheck.db 264B

str.index.db 233B

str.index.db 214B

str.index.db 182B

modfilename.db 157B

str.info.db 5B

vloganopts.db 4B

str.info.db 4B

vloganopts.db 4B

str.info.db 4B

vloganopts.db 4B

str.info.db 4B

vloganopts.db 4B

str.info.db 4B

vloganopts.db 4B

str.info.db 4B

vloganopts.db 4B

dumpcheck.db 0B

gtwizard_ultrascale_0.dcp 173KB

gtwizard_ultrascale_0_vio_0.dcp 134KB

simulate.do 9B

rtl.f 3KB

tb.f 42B

compile_simlib.log 266KB

.cxl.verilog.unisim.unisims_ver.lin64.log 111KB

.cxl.vhdl.unisim.unisim.lin64.log 103KB

.cxl.verilog.simprim.simprims_ver.lin64.log 34KB

vlogan.log 5KB

.cxl.verilog.secureip.secureip.lin64.log 2KB

共 308 条

################################################################################ # Vivado (TM) v2021.2 (64-bit) # # README.txt: Please read the sections below to understand the steps required # to simulate the design for a simulator, the directory structure # and the generated exported files. # ################################################################################ 1. Simulate Design To simulate design, cd to the simulator directory and execute the script. For example:- % cd questa % ./top.sh The export simulation flow requires the Xilinx pre-compiled simulation library components for the target simulator. These components are referred using the '-lib_map_path' switch. If this switch is specified, then the export simulation will automatically set this library path in the generated script and update, copy the simulator setup file(s) in the exported directory. If '-lib_map_path' is not specified, then the pre-compiled simulation library information will not be included in the exported scripts and that may cause simulation errors when running this script. Alternatively, you can provide the library information using this switch while executing the generated script. For example:- % ./top.sh -lib_map_path /design/questa/clibs Please refer to the generated script header 'Prerequisite' section for more details. 2. Directory Structure By default, if the -directory switch is not specified, export_simulation will create the following directory structure:- <current_working_directory>/export_sim/<simulator> For example, if the current working directory is /tmp/test, export_simulation will create the following directory path:- /tmp/test/export_sim/questa If -directory switch is specified, export_simulation will create a simulator sub-directory under the specified directory path. For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' command will create the following directory:- /tmp/test/my_test_area/func_sim/questa By default, if -simulator is not specified, export_simulation will create a simulator sub-directory for each simulator and export the files for each simulator in this sub-directory respectively. IMPORTANT: Please note that the simulation library path must be specified manually in the generated script for the respective simulator. Please refer to the generated script header 'Prerequisite' section for more details. 3. Exported script and files Export simulation will create the driver shell script, setup files and copy the design sources in the output directory path. By default, when the -script_name switch is not specified, export_simulation will create the following script name:- <simulation_top>.sh (Unix) When exporting the files for an IP using the -of_objects switch, export_simulation will create the following script name:- <ip-name>.sh (Unix) Export simulation will create the setup files for the target simulator specified with the -simulator switch. For example, if the target simulator is "xcelium", export_simulation will create the 'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' file.