5Intel
®
Virtualization Technology for Directed I/O Architecture Specification, Rev. 4.1, Order Number: D51397-016
Contents—Intel
®
Virtualization Technology for Directed I/O
6 Caching Translation Information ...............................................................................1
6.1 Caching Mode .....................................................................................................1
6.2 Address Translation Caches ..................................................................................1
6.2.1 Tagging of Cached Translations ..................................................................2
6.2.2 Context-Cache .........................................................................................3
6.2.2.1 Context-Entry Programming Considerations....................................4
6.2.3 PASID-Cache ...........................................................................................4
6.2.3.1 Scalable-Mode PASID-Table Entry Programming Considerations ........ 5
6.2.4 IOTLB.....................................................................................................5
6.2.4.1 Details of IOTLB Use ...................................................................7
6.2.5 Caches for Paging Structures .....................................................................8
6.2.5.1 PML5-cache ...............................................................................8
6.2.5.2 PML4-cache ...............................................................................9
6.2.5.3 PDPE-cache.............................................................................. 11
6.2.5.4 PDE-cache ............................................................................... 12
6.2.5.5 Details of Paging-Structure Cache Use ......................................... 13
6.2.6 Translating Address Using Caches in Legacy Mode ...................................... 14
6.2.7 Multiple Cached Entries for a Single Paging-Structure Entry.......................... 15
6.3 Translation Caching at Endpoint Device ................................................................ 15
6.4 Interrupt Entry Cache ........................................................................................ 15
6.5 Invalidation of Translation Caches ....................................................................... 16
6.5.1 Register-based Invalidation Interface ........................................................ 16
6.5.1.1 Context Command Register........................................................ 17
6.5.1.2 IOTLB Registers........................................................................ 17
6.5.2 Queued Invalidation Interface .................................................................. 18
6.5.2.1 Context-cache Invalidate Descriptor ............................................ 19
6.5.2.2 PASID-cache Invalidate Descriptor .............................................. 21
6.5.2.3 IOTLB Invalidate....................................................................... 22
6.5.2.4 PASID-based IOTLB Invalidate Descriptor (P_IOTLB) ..................... 25
6.5.2.5 Device-TLB Invalidate Descriptor ................................................ 26
6.5.2.6 PASID-based-Device-TLB Invalidate Descriptor ............................. 28
6.5.2.7 Interrupt Entry Cache Invalidate Descriptor.................................. 29
6.5.2.8 Invalidation Wait Descriptor ....................................................... 30
6.5.2.9 Hardware Generation of Invalidation Completion Events................. 31
6.5.2.10 Hardware Handling of Queued Invalidation Interface Errors ............ 32
6.5.2.11 Queued Invalidation Ordering Considerations................................ 33
6.5.3 Invalidation Considerations...................................................................... 33
6.5.3.1 Implicit Invalidation on Page Requests......................................... 33
6.5.3.2 Caching Fractured Translations ................................................... 34
6.5.3.3 Guidance to Software for Invalidations......................................... 34
6.5.3.4 Optional Invalidation ................................................................. 38
6.5.3.5 Delayed Invalidation ................................................................. 39
6.5.4 Draining of Requests to Memory............................................................... 40
6.5.5 Interrupt Draining .................................................................................. 40
6.6 Set Root Table Pointer Operation......................................................................... 41
6.7 Set Interrupt Remapping Table Pointer Operation .................................................. 42
6.8 Write Buffer Flushing ......................................................................................... 42
6.9 Hardware Register Programming Considerations.................................................... 42
6.10 Sharing Remapping Structures Across Hardware Units............................................ 43
7 Address Translation Faults ........................................................................................1
7.1 Remapping Hardware Behavior on Faults ................................................................1
7.1.1 Non-Recoverable Address Translation Faults ................................................1
7.1.2 Recoverable Address Translation Faults .......................................................1
7.1.3 Fault Conditions and Remapping Hardware Behavior for Various Requests........3
7.2 Non-Recoverable Fault Reporting......................................................................... 14
7.2.1 Primary Fault Logging ............................................................................. 14
