Multi-Root I/O Virtualization and Sharing Specification, Rev. 1.0
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3.1.5. VH and VF Mapping Policy.................................................................................. 91
3.1.6. VH and VF Mapping Implementation................................................................... 92
3.1.7. MR-PCIM Failover............................................................................................... 98
3.2. MR DEVICE INITIALIZATION.......................................................................................... 99
3.2.1. Enabling MR Operation...................................................................................... 100
3.2.2. Managing Flow Control ..................................................................................... 101
3.2.3. Managing VF Mapping....................................................................................... 101
3.2.4. Managing VF Migration..................................................................................... 104
3.3. MR ROOT PORT INITIALIZATION ................................................................................. 108
4. CONFIGURATION.......................................................................................................... 109
4.1. CONFIGURATION FIELD SUMMARY .............................................................................. 110
4.2. DEVICE CONFIGURATION SPACE.................................................................................. 119
4.2.1. Device MR-IOV Extended Capability................................................................. 120
4.2.2. Device VL Arbitration Table............................................................................... 136
4.2.3. LVF Table ........................................................................................................... 136
4.2.4. Function Table.................................................................................................... 137
4.2.5. Misc. Device Configuration Space Requirements .............................................. 151
4.3. SWITCH CONFIGURATION SPACE ................................................................................. 152
4.3.1. Switch MR-IOV Extended Capability ................................................................. 155
4.3.2. Switch VS Authorization Bitmap......................................................................... 163
4.3.3. Switch Port Table................................................................................................ 164
4.3.4. Switch VL Arbitration Table............................................................................... 184
4.3.5. Switch VS Table .................................................................................................. 184
4.3.6. Switch VS Bridge Table ...................................................................................... 188
4.3.7. Miscellaneous Switch Configuration Space Requirements................................. 202
4.4. VL ARBITRATION TABLE............................................................................................. 208
4.5. PERFORMANCE MONITORING AND STATISTICS COLLECTION....................................... 209
4.5.1. Configuration Space Fields ................................................................................ 211
4.5.2. Statistics Descriptor Table.................................................................................. 214
4.5.3. Statistics Block Table.......................................................................................... 221
4.5.4. Statistics Counter Table...................................................................................... 222
5. ERROR HANDLING....................................................................................................... 225
5.1. PCIE ERROR MAPPING TO MR..................................................................................... 225
5.2. MR ERRORS................................................................................................................. 228
6. HOT PLUG........................................................................................................................ 231
6.1. MRA SWITCH.............................................................................................................. 231
6.1.1. PCI Express Capability: Slot Capability Register.............................................. 232
6.1.2. PCI Express Capability: Slot Control Register .................................................. 233
6.1.3. PCI Express Capability: Slot Status Register..................................................... 235
6.1.4. PCI Express Capability: PCI Express Capabilities Register............................. 236
6.1.5. Hot-Plug Virtual Signals Interface Registers ..................................................... 237
6.1.6. Physical Slot Registers........................................................................................ 238
6.1.7. Physical Hot-Plug Signals Interface................................................................... 238
6.2. VIRTUAL DEVICE MIGRATION ..................................................................................... 238
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