Altera Corporation 1
AN-398-1.1 Preliminary
Application Note 398
Using DDR/DDR2 SDRAM
With SOPC Builder
Introduction
The DDR/DDR2 SDRAM Controller MegaCore
®
function version 3.4.0
and later supports SOPC Builder, enabling the function to instantiate a
DDR/DDR2 SDRAM Controller inside an SOPC Builder system.
This application note discusses the following topics:
■ Implementing a DDR2 SDRAM Controller within SOPC Builder
■ Incorporating a Nios
®
II processor and other peripherals
■ Compiling the design and generating the programming file
■ Downloading the design to a board and running sample code on
your design in hardware to test the read and write transactions
1 The example design is targeted to the Cyclone
®
II device family.
You can also use these procedures for other supported device
families.
Requirements
This application note requires the following hardware and software:
■ An Altera
®
development board with DDR or DDR2 SDRAM
memory, such as a Cyclone II DSP development board
■ DDR/DDR2 SDRAM Controller MegaCore function version 3.4.0 or
later
■ Quartus
®
II software version 6.0 or later
f For more information about the Altera DDR/DDR2 memory controllers,
refer to the DDR & DDR2 SDRAM Controller Compiler User Guide.
Setting Up the SOPC Builder Project
To create and run an SOPC Builder project, perform the following tasks:
■ “Create a New Quartus II Project” on page 2
■ “Create the SOPC Builder System” on page 4
■ “Create the Top-Level Verilog HDL File” on page 22
■ “Update the Quartus II Project Settings” on page 32
■ “Set Up the SignalTap II Logic Analyzer” on page 33
■ “Compile the Project” on page 39
■ “Verify the Timing Results” on page 39
August 2006, ver. 1.1
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资源评论
twinsheros2013-09-11虽是官方的资料，但翻译的很精准，获益匪浅，里头有些细节跟具体的FPGA开发板是有关系的，这部分还是没看明白- snowolf1234562013-12-14官方的datasheet，意义不大
- ll1245711172013-05-23就是官方的资料啊
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