Computer Architecture 2022-23
Assessed Exercise 1
— State Machine Circuit —
Introduction
The purposes of this exercise are to learn how to design a simple synchronous
digital circuit that implements a state machine, how to specify it in a hardware
description language, and how to test it via simulation. The specification and
simulation will use Hydra, a functional computer hardware description language.
The exercise
Design and implement
• Two circuits, as described below, which should all be in a file Traffi-
cLight.hs.
• A simulation driver for each circuit; both of these should be in a file named
TrafficLightRun.hs
• Suitable test data that demonstrates the correct functioning of each cir-
cuit, which should be included in TrafficLightRun.hs.
• There should be a main function in TrafficLightRun.hs that runs all of
your test cases.
Informal specification of the circuit
The circuits are traffic light controllers. There are two versions.
Version 1
The circuit controller1 has one input, a bit called reset. This would be connected
to a pushbutton. The reset button should be pushed once to start the circuit,
and then in normal use it would never be pressed again. We model this by
defining the value of the reset input bit to be 1 during the first clock cycle, and
0 thereafter.
There are three outputs, each of which is a bit. The outputs correspond to
green, amber, and red, and they determine whether the corresponding traffic
light is on. At all times (after reset has been pressed and the circuit is running)
one of the three output bits should be 1, indicating that the corresponding traffic
light should be on, and the other two bits should be 0. The outputs should run
through a fixed sequence: green, green, green, amber, red, red, red, red, amber,
and then it repeats.
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