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INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986

Page 1 of 421

INTEL 80386

PROGRAMMER'S REFERENCE MANUAL

1986

Intel Corporation makes no warranty for the use of its products and

assumes no responsibility for any errors which may appear in this document

nor does it make a commitment to update the information contained herein.

Intel retains the right to make changes to these specifications at any

time, without notice.

Contact your local sales office to obtain the latest specifications before

placing your order.

The following are trademarks of Intel Corporation and may only be used to

identify Intel Products:

Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius, i, î,

ICE, iCEL, iCS, iDBP, iDIS, I²ICE, iLBX, im, iMDDX, iMMX, Inboard,

Insite, Intel, intel, intelBOS, Intel Certified, Intelevision,

inteligent Identifier, inteligent Programming, Intellec, Intellink,

iOSP, iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, Library

Manager, MAPNET, MCS, Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL,

MULTIMODULE, MultiSERVER, ONCE, OpenNET, OTP, PC BUBBLE, Plug-A-Bubble,

PROMPT, Promware, QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80,

RUPI, Seamless, SLD, SugarCube, SupportNET, UPI, and VLSiCEL, and the

combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a numerical

suffix, 4-SITE.

MDS is an ordering code only and is not used as a product name or

trademark. MDS(R) is a registered trademark of Mohawk Data Sciences

Corporation.

Additional copies of this manual or other Intel literature may be obtained

from:

Intel Corporation

Literature Distribution

Mail Stop SC6-59

3065 Bowers Avenue

Santa Clara, CA 95051

INTEL CORPORATION 1987 CG-5/26/87

Edited 2001-02-01 by G.N.

INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986

Page 2 of 421

Customer Support

───────────────────────────────────────────────────────────────────────────

Customer Support is Intel's complete support service that provides Intel

customers with hardware support, software support, customer training, and

consulting services. For more information contact your local sales offices.

After a customer purchases any system hardware or software product,

service and support become major factors in determining whether that

product will continue to meet a customer's expectations. Such support

requires an international support organization and a breadth of programs

to meet a variety of customer needs. As you might expect, Intel's customer

support is quite extensive. It includes factory repair services and

worldwide field service offices providing hardware repair services,

software support services, customer training classes, and consulting

services.

Hardware Support Services

Intel is committed to providing an international service support package

through a wide variety of service offerings available from Intel Hardware

Support.

Software Support Services

Intel's software support consists of two levels of contracts. Standard

support includes TIPS (Technical Information Phone Service), updates and

subscription service (product-specific troubleshooting guides and COMMENTS

Magazine). Basic support includes updates and the subscription service.

Contracts are sold in environments which represent product groupings

(i.e., iRMX environment).

Consulting Services

Intel provides field systems engineering services for any phase of your

development or support effort. You can use our systems engineers in a

variety of ways ranging from assistance in using a new product, developing

an application, personalizing training, and customizing or tailoring an

Intel product to providing technical and management consulting. Systems

Engineers are well versed in technical areas such as microcommunications,

real-time applications, embedded microcontrollers, and network services.

You know your application needs; we know our products. Working together we

can help you get a successful product to market in the least possible time.

Customer Training

Intel offers a wide range of instructional programs covering various

aspects of system design and implementation. In just three to ten days a

limited number of individuals learn more in a single workshop than in

weeks of self-study. For optimum convenience, workshops are scheduled

regularly at Training Centers woridwide or we can take our workshops to

you for on-site instruction. Covering a wide variety of topics, Intel's

major course categories include: architecture and assembly language,

programming and operating systems, bitbus and LAN applications.

INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986

Page 4 of 421

Table of Contents

CUSTOMER SUPPORT......................................................................................................................................... 2

CHAPTER 1 INTRODUCTION TO THE 80386 .............................................................................................. 15

1.1 O

RGANIZATION OF

HIS

ANUAL

................................................................................................................. 15

1.1.1 Part I ── Applications Programming ................................................................................................... 16

1.1.2 Part II ── Systems Programming ......................................................................................................... 17

1.1.3 Part III ── Compatibility...................................................................................................................... 18

1.1.4 Part IV ── Instruction Set..................................................................................................................... 18

1.1.5 Appendices ............................................................................................................................................. 18

1.2 R

ELATED

ITERATURE

................................................................................................................................... 19

1.3 N

OTATIONAL

ONVENTIONS

......................................................................................................................... 19

1.3.1 Data-Structure Formats......................................................................................................................... 19

1.3.2 Undefined Bits and Software Compatibility........................................................................................... 19

1.3.3 Instruction Operands ............................................................................................................................. 20

1.3.4 Hexadecimal Numbers ........................................................................................................................... 21

1.3.5 Sub- and Super-Scripts........................................................................................................................... 21

CHAPTER 2 BASIC PROGRAMMING MODEL............................................................................................ 22

2.1 M

EMORY

RGANIZATION AND

EGMENTATION

............................................................................................ 22

2.1.1 The "Flat" Model ................................................................................................................................... 23

2.1.2 The Segmented Model ............................................................................................................................ 23

2.2 D

ATA

YPES

.................................................................................................................................................. 24

2.3 R

EGISTERS

..................................................................................................................................................... 29

2.3.1 General Registers................................................................................................................................... 29

2.3.2 Segment Registers .................................................................................................................................. 30

2.3.3 Stack Implementation............................................................................................................................. 32

2.3.4 Flags Register ........................................................................................................................................ 33

2.3.4.1 Status Flags ....................................................................................................................................................... 34

2.3.4.2 Control Flag....................................................................................................................................................... 34

2.3.4.3 Instruction Pointer ............................................................................................................................................. 35

2.4 I

NSTRUCTION

ORMAT

.................................................................................................................................. 35

2.5 O

PERAND

ELECTION

.................................................................................................................................... 36

2.5.1 Immediate Operands.............................................................................................................................. 37

2.5.2 Register Operands ................................................................................................................................. 38

2.5.3 Memory Operands ................................................................................................................................. 38

2.5.3.1 Segment Selection ............................................................................................................................................. 39

2.5.3.2 Effective-Address Computation ........................................................................................................................ 40

2.6 I

NTERRUPTS AND

XCEPTIONS

....................................................................................................................... 42

CHAPTER 3 APPLICATIONS INSTRUCTION SET ..................................................................................... 45

3.1 D

ATA

OVEMENT

NSTRUCTIONS

................................................................................................................. 45

3.1.1 General-Purpose Data Movement Instructions ..................................................................................... 45

3.1.2 Stack Manipulation Instructions ............................................................................................................ 46

3.1.3 Type Conversion Instructions ................................................................................................................ 48

3.2 B

INARY

RITHMETIC

NSTRUCTIONS

............................................................................................................. 50

3.2.1 Addition and Subtraction Instructions ................................................................................................... 51

3.2.2 Comparison and Sign Change Instruction............................................................................................. 51

3.2.3 Multiplication Instructions..................................................................................................................... 51

3.2.4 Division Instructions.............................................................................................................................. 52

3.3 D

ECIMAL

RITHMETIC

NSTRUCTIONS

.......................................................................................................... 53

3.3.1 Packed BCD Adjustment Instructions.................................................................................................... 53

3.3.2 Unpacked BCD Adjustment Instructions................................................................................................ 54

3.4 L

OGICAL

NSTRUCTIONS

................................................................................................................................54

INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986

Page 5 of 421

3.4.1 Boolean Operation Instructions............................................................................................................. 54

3.4.2 Bit Test and Modify Instructions............................................................................................................ 55

3.4.3 Bit Scan Instructions .............................................................................................................................. 55

3.4.4 Shift and Rotate Instructions.................................................................................................................. 56

3.4.4.1 Shift Instructions ............................................................................................................................................... 56

3.4.4.2 Double-Shift Instructions .................................................................................................................................. 58

3.4.4.3 Rotate Instructions............................................................................................................................................. 59

3.4.4.4 Fast "BIT BLT" Using Double Shift Instructions.............................................................................................. 61

3.4.4.5 Fast Bit-String Insert and Extract ...................................................................................................................... 61

3.4.5 Byte-Set-On-Condition Instructions....................................................................................................... 64

3.4.6 Test Instruction ...................................................................................................................................... 64

3.5 C

ONTROL

RANSFER

NSTRUCTIONS

............................................................................................................. 65

3.5.1 Unconditional Transfer Instructions...................................................................................................... 65

3.5.1.1 Jump Instruction................................................................................................................................................ 65

3.5.1.2 Call Instruction.................................................................................................................................................. 66

3.5.1.3 Return and Return-From-Interrupt Instruction .................................................................................................. 66

3.5.2 Conditional Transfer Instructions.......................................................................................................... 66

3.5.2.1 Conditional Jump Instructions........................................................................................................................... 67

3.5.2.2 Loop Instructions............................................................................................................................................... 67

3.5.2.3 Executing a Loop or Repeat Zero Times ........................................................................................................... 68

3.5.3 Software-Generated Interrupts .............................................................................................................. 68

3.6 S

TRING AND

HARACTER

RANSLATION

NSTRUCTIONS

............................................................................... 69

3.6.1 Repeat Prefixes ...................................................................................................................................... 70

3.6.2 Indexing and Direction Flag Control .................................................................................................... 71

3.6.3 String Instructions.................................................................................................................................. 71

3.7 I

NSTRUCTIONS FOR

LOCK

-S

TRUCTURED

ANGUAGES

................................................................................. 72

3.8 F

LAG

ONTROL

NSTRUCTIONS

..................................................................................................................... 79

3.8.1 Carry and Direction Flag Control Instructions..................................................................................... 79

3.8.2 Flag Transfer Instructions ..................................................................................................................... 79

3.9 C

OPROCESSOR

NTERFACE

NSTRUCTIONS

..................................................................................................... 80

3.10 S

EGMENT

EGISTER

NSTRUCTIONS

............................................................................................................ 81

3.10.1 Segment-Register Transfer Instructions............................................................................................... 82

3.10.2 Far Control Transfer Instructions ....................................................................................................... 82

3.10.3 Data Pointer Instructions..................................................................................................................... 82

3.11 M

ISCELLANEOUS

NSTRUCTIONS

................................................................................................................. 83

3.11.1 Address Calculation Instruction .......................................................................................................... 83

3.11.2 No-Operation Instruction..................................................................................................................... 84

3.11.3 Translate Instruction............................................................................................................................ 84

CHAPTER 4 SYSTEMS ARCHITECTURE ..................................................................................................... 85

4.1 S

YSTEMS

EGISTERS

..................................................................................................................................... 85

4.1.1 Systems Flags......................................................................................................................................... 85

4.1.2 Memory-Management Registers ............................................................................................................ 87

4.1.3 Control Registers ................................................................................................................................... 87

4.1.4 Debug Register....................................................................................................................................... 88

4.1.5 Test Registers ......................................................................................................................................... 89

4.2 S

YSTEMS

NSTRUCTIONS

................................................................................................................................89

CHAPTER 5 MEMORY MANAGEMENT ....................................................................................................... 91

5.1 S

EGMENT

RANSLATION

............................................................................................................................... 92

5.1.1 Descriptors............................................................................................................................................. 92

5.1.2 Descriptor Tables................................................................................................................................... 94

5.1.3 Selectors................................................................................................................................................. 96

5.1.4 Segment Registers .................................................................................................................................. 97

5.2 P

AGE

RANSLATION

...................................................................................................................................... 98

5.2.1 Page Frame............................................................................................................................................ 98

5.2.2 Linear Address....................................................................................................................................... 98