Zynq7000_SoC_IEEE1588_PTP_design-linux实现

/* * Xilinx Ethernet: Linux driver for Ethernet. * * Author: Xilinx, Inc. * * 2010 (c) Xilinx, Inc. This file is licensed uner the terms of the GNU * General Public License version 2. This program is licensed "as is" * without any warranty of any kind, whether express or implied. * * This is a driver for xilinx processor sub-system (ps) ethernet device. * This driver is mainly used in Linux 2.6.30 and above and it does _not_ * support Linux 2.4 kernel due to certain new features (e.g. NAPI) is * introduced in this driver. * * TODO: * 1. JUMBO frame is not enabled per EPs spec. Please update it if this * support is added in and set MAX_MTU to 9000. * 2. PTP slave mode: Findout and implement the proper equation and algorithm * for adjusting the hw timer frequency inorder to sync with the master * clock offset. Also formula for deriving the max adjustable frequency * value in ppb. */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/mm.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/platform_device.h> #include <linux/phy.h> #include <linux/mii.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/ethtool.h> #include <linux/vmalloc.h> #include <linux/version.h> #include <linux/of.h> #include <linux/interrupt.h> #include <linux/clocksource.h> #include <linux/net_tstamp.h> #include <linux/pm_runtime.h> #include <linux/clk.h> #include <linux/of_net.h> #include <linux/of_address.h> #include <linux/of_mdio.h> #include <linux/timer.h> #include <linux/ptp_clock_kernel.h> /************************** Constant Definitions *****************************/ /* Must be shorter than length of ethtool_drvinfo.driver field to fit */ #define DRIVER_NAME "xemacps" #define DRIVER_DESCRIPTION "Xilinx Tri-Mode Ethernet MAC driver" #define DRIVER_VERSION "1.00a" /* Transmission timeout is 3 seconds. */ #define TX_TIMEOUT (3*HZ) /* for RX skb IP header word-aligned */ #define RX_IP_ALIGN_OFFSET 2 /* DMA buffer descriptors must be aligned on a 4-byte boundary. */ #define ALIGNMENT_BD 8 /* Maximum value for hash bits. 2**6 */ #define XEMACPS_MAX_HASH_BITS 64 /* MDC clock division * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. */ enum { MDC_DIV_8 = 0, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 }; /* Specify the receive buffer size in bytes, 64, 128, 192, 10240 */ #define XEMACPS_RX_BUF_SIZE 1536 /* Number of receive buffer bytes as a unit, this is HW setup */ #define XEMACPS_RX_BUF_UNIT 64 /* Default SEND and RECV buffer descriptors (BD) numbers. * BD Space needed is (XEMACPS_SEND_BD_CNT+XEMACPS_RECV_BD_CNT)*8 */ #undef DEBUG #define DEBUG #define XEMACPS_SEND_BD_CNT 256 #define XEMACPS_RECV_BD_CNT 256 #define XEMACPS_NAPI_WEIGHT 64 /* Register offset definitions. Unless otherwise noted, register access is * 32 bit. Names are self explained here. */ #define XEMACPS_NWCTRL_OFFSET 0x00000000 /* Network Control reg */ #define XEMACPS_NWCFG_OFFSET 0x00000004 /* Network Config reg */ #define XEMACPS_NWSR_OFFSET 0x00000008 /* Network Status reg */ #define XEMACPS_USERIO_OFFSET 0x0000000C /* User IO reg */ #define XEMACPS_DMACR_OFFSET 0x00000010 /* DMA Control reg */ #define XEMACPS_TXSR_OFFSET 0x00000014 /* TX Status reg */ #define XEMACPS_RXQBASE_OFFSET 0x00000018 /* RX Q Base address reg */ #define XEMACPS_TXQBASE_OFFSET 0x0000001C /* TX Q Base address reg */ #define XEMACPS_RXSR_OFFSET 0x00000020 /* RX Status reg */ #define XEMACPS_ISR_OFFSET 0x00000024 /* Interrupt Status reg */ #define XEMACPS_IER_OFFSET 0x00000028 /* Interrupt Enable reg */ #define XEMACPS_IDR_OFFSET 0x0000002C /* Interrupt Disable reg */ #define XEMACPS_IMR_OFFSET 0x00000030 /* Interrupt Mask reg */ #define XEMACPS_PHYMNTNC_OFFSET 0x00000034 /* Phy Maintaince reg */ #define XEMACPS_RXPAUSE_OFFSET 0x00000038 /* RX Pause Time reg */ #define XEMACPS_TXPAUSE_OFFSET 0x0000003C /* TX Pause Time reg */ #define XEMACPS_HASHL_OFFSET 0x00000080 /* Hash Low address reg */ #define XEMACPS_HASHH_OFFSET 0x00000084 /* Hash High address reg */ #define XEMACPS_LADDR1L_OFFSET 0x00000088 /* Specific1 addr low */ #define XEMACPS_LADDR1H_OFFSET 0x0000008C /* Specific1 addr high */ #define XEMACPS_LADDR2L_OFFSET 0x00000090 /* Specific2 addr low */ #define XEMACPS_LADDR2H_OFFSET 0x00000094 /* Specific2 addr high */ #define XEMACPS_LADDR3L_OFFSET 0x00000098 /* Specific3 addr low */ #define XEMACPS_LADDR3H_OFFSET 0x0000009C /* Specific3 addr high */ #define XEMACPS_LADDR4L_OFFSET 0x000000A0 /* Specific4 addr low */ #define XEMACPS_LADDR4H_OFFSET 0x000000A4 /* Specific4 addr high */ #define XEMACPS_MATCH1_OFFSET 0x000000A8 /* Type ID1 Match reg */ #define XEMACPS_MATCH2_OFFSET 0x000000AC /* Type ID2 Match reg */ #define XEMACPS_MATCH3_OFFSET 0x000000B0 /* Type ID3 Match reg */ #define XEMACPS_MATCH4_OFFSET 0x000000B4 /* Type ID4 Match reg */ #define XEMACPS_WOL_OFFSET 0x000000B8 /* Wake on LAN reg */ #define XEMACPS_STRETCH_OFFSET 0x000000BC /* IPG Stretch reg */ #define XEMACPS_SVLAN_OFFSET 0x000000C0 /* Stacked VLAN reg */ #define XEMACPS_MODID_OFFSET 0x000000FC /* Module ID reg */ #define XEMACPS_OCTTXL_OFFSET 0x00000100 /* Octects transmitted Low reg */ #define XEMACPS_OCTTXH_OFFSET 0x00000104 /* Octects transmitted High reg */ #define XEMACPS_TXCNT_OFFSET 0x00000108 /* Error-free Frmaes transmitted counter */ #define XEMACPS_TXBCCNT_OFFSET 0x0000010C /* Error-free Broadcast Frames counter*/ #define XEMACPS_TXMCCNT_OFFSET 0x00000110 /* Error-free Multicast Frame counter */ #define XEMACPS_TXPAUSECNT_OFFSET 0x00000114 /* Pause Frames Transmitted Counter */ #define XEMACPS_TX64CNT_OFFSET 0x00000118 /* Error-free 64 byte Frames Transmitted counter */ #define XEMACPS_TX65CNT_OFFSET 0x0000011C /* Error-free 65-127 byte Frames Transmitted counter */ #define XEMACPS_TX128CNT_OFFSET 0x00000120 /* Error-free 128-255 byte Frames Transmitted counter */ #define XEMACPS_TX256CNT_OFFSET 0x00000124 /* Error-free 256-511 byte Frames transmitted counter */ #define XEMACPS_TX512CNT_OFFSET 0x00000128 /* Error-free 512-1023 byte Frames transmitted counter */ #define XEMACPS_TX1024CNT_OFFSET 0x0000012C /* Error-free 1024-1518 byte Frames transmitted counter */ #define XEMACPS_TX1519CNT_OFFSET 0x00000130 /* Error-free larger than 1519 byte Frames transmitted Counter */ #define XEMACPS_TXURUNCNT_OFFSET 0x00000134 /* TX under run error Counter */ #define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138 /* Single Collision Frame Counter */ #define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013C /* Multiple Collision Frame Counter */ #define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140 /* Excessive Collision Frame Counter */ #define XEMACPS_LATECOLLCNT_OFFSET 0x00000144 /* Late Collision Frame Counter */ #define XEMACPS_TXDEFERCNT_OFFSET 0x00000148 /* Deferred Transmission Frame Counter */ #define XEMACPS_CSENSECNT_OFFSET 0x0000014C /* Carrier Sense Error Counter */ #define XEMACPS_OCTRXL_OFFSET 0x00000150 /* Octects Received register Low */ #define XEMACPS_OCTRXH_OFFSET 0x00000154 /* Octects Received register High */ #define XEMACPS_RXCNT_OFFSET 0x00000158 /* Error-free Frames Received Counter */ #define XEMACPS_RXBROADCNT_OFFSET 0x0000015C /* Error-free Broadcast Frames Received Counter */ #define XEMACPS_RXMULTICNT_OFFSET 0x00000160 /* Error-free Multicast Frames Received Counter */ #define XEMACPS_RXPAUSECNT_OFFSET 0x00000164 /* Pause Frames Received Counter */ #define XEMACPS_RX64CNT_OFFSET 0x00000168 /* Error-free 64 byte Frames Received Counter */ #define XEMACPS_RX65CNT_OFFSET 0x0000016C /* Error-free 65-127 byte Frames Received Counter */ #define XEMACPS_RX128CNT_OFFSET 0x00000170 /* Error-free 128-255 byte Frames Rece