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Zynq-7000
All Programmable SoC
Technical Reference Manual
UG585 (v1.7) February 11, 2014
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 2
UG585 (v1.7) February 11, 2014
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with,
the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such
damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct
any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce,
modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions
of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm
; IP cores may be subject to warranty and support
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http://www.xilinx.com/warranty.htm#critapps
.
© Copyright 2012–2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included
herein are trademarks of Xilinx in the United States and other countries. CPRI is a trademark of Siemens AG. PCI, PCI Express, PCIe, and PCI-X
are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.
Revision History
The following table shows the revision history for this document. Change bars indicate the latest revisions.
Date Version Revision
04/08/2012 1.0 Xilinx initial release.
06/25/2012 1.1 Removed Chapter 30, Board Design (now part of UG933, Zynq-7000 All Programmable
SoC PCB Design and Pin Planning Guide).
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 3
UG585 (v1.7) February 11, 2014
08/08/2012 1.2 Added information about the 7z010 CLG225 device and references to section
2.5.4 MIO-at-a-Glance Table throughout document.
Added section headings
1.1.1 Block Diagram and 1.1.2 Documentation Resources, added sections 1.1.3 Notices
and TrustZone Capabilities, and clarified PS MIO I/Os in Chapter 1. Updated Table 2-1.
Changed 2.4.2 MIO-EMIO Connections heading to 2.5.2 IOP Interface Connections and
clarified first paragraph. Updated Table 2-4. Added section 2.7.1 Clocks and Resets and
Table 2-7, and updated Table 2-13 PS MIO I/Os in Chapter 2. Added note under Branch
Prediction and Table 3-8 in Chapter 3. Updated Table 4-1 in Chapter 4. Added section
5.1.7 Read/Write Request Capability in Chapter 5. Updated
NAND Boot MIO pin
assignments and
Table 6-6 in Chapter 6. Updated section 7.1.5 CPU Interrupt Signal
Pass-through in Chapter 7. Added section heading 10.1.1 Features and added section
10.1.3 Notices in Chapter 10. Updated Parallel (SRAM/NOR) Interface features list and
added section 11.1.3 Notices in Chapter 11. Reorganized, clarified, and expanded
Chapter 12 to include programming models (added sections 12.1.4 Notices,
12.3 Programming Guide, and 12.5.2 MIO Programming). Added last note in section
13.3.4 Using ADMA in Chapter 13. Added Restrictions in Chapter 14. Clarified first
paragraph, added section 15.1.3 Notices, and clarified Figure 15-7 through
Figure 15-17 in Chapter 15. Added section 16.1.4 Notices in Chapter 16. Clarified
sections 17.2.5 SPI FIFOs, 17.2.6 SPI Clocks, and 17.2.7 SPI EMIO Considerations in
Chapter 17. Reorganized, clarified, and expanded Chapter 18 to include programming
models (added sections 18.1.4 Notices and 18.5.1 MIO Programming). Reorganized,
clarified, and expanded Chapter 19 to include programming models (added sections
19.1.3 Notices, 19.3 Programming Guide, and 19.5.1 MIO Programming). Updated
Table 22-2 and Table 22-3 in Chapter 22. Added section CPU Clock Divisor Restriction in
Chapter 25. Updated Table 26-4 in Chapter 26. Clarified section 27.3 I/O Signals in
Chapter 27. Added section 28.1.2 Notices in Chapter 28. Clarified Mapping Summary
and updated
Table 29-1, Table 29-3, and Ta b l e 29-5 in Chapter 29. Added section
30.1.3 Notices in Chapter 30. Updated data sheet references in section A.3.1 Zynq-7000
AP SoC Documents of Appendix A. Updated register database in sections B.3 Module
Summary through B.34 USB Controller (usb) in Appendix B.
10/30/2012 1.3 Changed product name from Extensible Processing Platform (EPP) to All Programmable
SoC (AP SoC) throughout document. Added Ta b l e 1-1. Added 2.1.1 Notices, 2.4 PS–PL
Voltage Level Shifter Enables, A summary of the dedicated PS signal pins is shown in
Table 2-2., VREF Source Considerations, updated Table 2 - 2 , and added warning to
2.5.7 MIO Pin Electrical Parameters. Added Initialization of L1 Caches, 3.2.4 Memory
Ordering, expanded 3.2.5 Memory Management Unit (MMU), added Cache Lockdown
by Way Sequence and 3.9 CPU Initialization Sequence. Added Zynq-7000 AP SoC 7z010
CLG225 Device Notice and expanded Table 4-7. Updated and expanded tables in
6.3.4 Quad-SPI Boot through 6.3.12 Post BootROM State, reworked 6.3.6 Debug Status,
and added 6.3.12 Post BootROM State and AXI and DMA Done Status Interrupts.
Reworked Table 7-3. Added 8.1.2 Notices, Interrupt to PS Interrupt Controller, and
Reset. Reorganized and expanded Chapter 9, DMA Controller. Added 10.1.3 Notices,
expanded 10.1.6 I/O Signals, added 10.6.11 DRAM Write Latency Restriction,
10.8.1 ECC Initialization, 10.8.4 ECC Programming Model, and 10.9.1 Operating Modes.
Added 12.2.4 I/O Mode Considerations and updated 12.3.5 Rx/Tx FIFO Response to I/O
Command Sequences
. Reworked 16.3.3 I/O Configuration, added 16.4 IEEE 1588 Time
Stamping and 16.6.7 MIO Pin Considerations. Added 18.2.7 CAN0-to-CAN1
Connection. Expanded 19.1 Introduction, 19.1.3 Notices, and Table 19-1. Added
Receiver Timeout Mechanism, updated Figure 19-7. Added 19.2.9 UART0-to-UART1
Connection and 19.2.10 Status and Interrupts, expanded 19.2.11 Modem Control,
reworked 19.3 Programming Guide and 19.4.2 Resets. Added 20.2.7 I2C0-to-I2C1
Connection. Added 21.1.2 PL Resources by Device Type, Voltage Level Shifters and
reorganized content of Chapter 21, Programmable Logic Description. Added
25.7.1 Clock Throttle. Expanded 26.4.1 PL General Purpose User Resets. Updated
register database in sections B.3 Module Summary through B.34 USB Controller (usb)
in Appendix B.
11/16/2012 1.4 Changed second bullet under NAND Flash Interface from “
Up to a 4 GB device” to “Up
to a 1 GB device” in
Chapter 11, Static Memory Controller.
Date Version Revision
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 4
UG585 (v1.7) February 11, 2014
03/07/2013 1.5 Added 7z100 device and made minor clarifications to Chapter 1, Introduction. Made
minor clarifications to Chapter 2, Signals, Interfaces, and Pins, Chapter 3, Application
Processing Unit, Chapter 4, System Addresses, and Chapter 5, Interconnect. Clarified
section 6.1 Introduction and other sections, and added PS Independent JTAG
Non-Secure Boot section in Chapter 6, Boot and Configuration. Made minor
clarifications to Chapter 7, Interrupts, Chapter 8, Timers, Chapter 9, DMA Controller,
Chapter 10, DDR Memory Controller, Chapter 11, Static Memory Controller, and
Chapter 12, Quad-SPI Flash Controller. Expanded 12.2 Functional Description in
Chapter 12, Quad-SPI Flash Controller. Made minor clarifications to Chapter 13,
SD/SDIO Controller. Made major clarifications/updates to Chapter 14, General Purpose
I/O (GPIO). Reworked and expanded Chapter 15, USB Host, Device, and OTG Controller.
Made minor clarifications to Chapter 16, Gigabit Ethernet Controller. Reworked and
expanded Chapter 17, SPI Controller. Made minor clarifications to Chapter 18, CAN
Controller, and Chapter 19, UART Controller. Made major clarifications/updates to
Chapter 20, I2C Controller (added new sections, 20.3 Programmer’s Guide, 20.4 System
Functions, and 20.5 I/O Interface). Made minor clarifications to Chapter 21,
Programmable Logic Description and added new sections 21.1.2 PL Resources by Device
Type and 21.1.3 Notices. Made minor clarifications to Chapter 22, Programmable Logic
Design Guide and Chapter 23, Programmable Logic Test and Debug. Reworked and
expanded Chapter 24, Power Management. Made minor clarifications to Chapter 25,
Clocks, Chapter 26, Reset System, Chapter 27, JTAG and DAP Subsystem, Chapter 28,
System Test and Debug, and Chapter 29, On-Chip Memory (OCM). Reworked and
expanded Chapter 30, XADC Interface. Made minor clarifications to Chapter 31, PCI
Express. Reworked and expanded
Chapter 32, Device Secure Boot. Updated Appendix A,
Additional Resources. Updated register database in sections B.3 Module Summary
through B.34 USB Controller (usb) in Appendix B.
Date Version Revision
Zynq-7000 AP SoC Technical Reference Manual www.xilinx.com 5
UG585 (v1.7) February 11, 2014
06/28/13 1.6 Added icons where applicable. Enhanced first sentence under Quad-SPI Controller in c.
Clarified first paragraph, added step 2, and clarified step 5 in section 2.4 PS–PL Voltage
Level Shifter Enables. Changed “drive strength” to “slew rate” in section 2.5.7 MIO Pin
Electrical Parameters. Added second sentence and updated Table 2-11 in section
2.7.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals. Corrected Note 4 in Table 4 -1
and Table 4-2. Made minor clarifications and added new RSA Authentication Time
section to Chapter 6, Boot and Configuration. Made minor clarifications to sections
7.2.2 CPU Private Peripheral Interrupts (PPI) and 7.2.3 Shared Peripheral Interrupts
(SPI), and updated Table 7 - 3 and Table 7 - 4. Clarified first row in Table 9- 12. Added tip
to section 10.4.3 Aging Counter, added sentence to Write Leveling, and step 2 in section
10.9.2 Changing Clock Frequencies, and moved section 10.9.6 DDR Power Reduction
from Chapter 24, Power Management to this chapter. Added tip to section
11.2.2 Clocks. Added Ta ble 12-8. Added
MMC3.31 standard information to section
13.1 Introduction. Added step 6 to section 14.3.1 Start-up Sequence, added section
14.3.5 GPIO as Wake-up Event, added second paragraph to 14.4.1 Clocks. Added
section 16.7 Known Issues. Added note to 17.4.2 Clocks. Changed value of 107 Mb to
140 Mb in second sentence under section 21.4 Configuration. Added values for the
7z100 device in Table 2 1-2. Clarified first paragraph in section 24.2.2 PL Power-down
Control and updated Table 24-2. Added note to section 25.6.1 USB Clocks, clarified
second paragraph in section 25.10.4 PLLs, and added sentence to steps 2 and 3 in
Software-Controlled PLL Update section. Changed “RESET_REASON” to
“REBOOT_STAUTS in section 26.2.3 System Software Reset, added section
26.4.2 AXI/DMA Interface Resets, deleted first two rows from Table 26-2 and modified
last paragraph in section 26.5.1 Reset Subsystem Control and Status. Clarified section
29.1 Introduction, added three paragraphs to Starvation Scenarios section, and added
Address Mapping heading. Corrected spelling of “MCTRL” to “MCTL” in sections
30.4 Programming Guide for the PS-XADC Interface and 30.7.2 Resets. Added section
31.5 Root Complex Use Case. Added FIPS standards and clarified section
32.1.2 Features, updated configuration file and secure boot process steps in
Figure 32-1, added boot time penalty to Power on Reset section, changed “Secure Boot”
heading to ”Secure FSBL Decryption”, changed “ROM code” to “OCM ROM Memory” in
Figure 32-2 and “ROM” to “OCM ROM” in Table 32-3, updated sections 32.2.7 Boot
Image and Bitstream Decryption and Authentication, 32.2.8 HMAC Signature,
32.2.9 AES Key Management, 32.3.1 Non-Secure Boot State, 32.3.4 Boot Partition
Search, and 32.3.7 Secure Boot Modes of Operation (deleted Table 32-4, “Non-secure
Boot Options”). Updated register database in sections B.3 Module Summary through
B.34 USB Controller (usb) in Appendix B.
02/11/2014 1.7 Added 7z015 device, updated device notices, and made minor clarifications throughout
document (denoted with change bars). Added section 3.10 Implementation-Defined
Configurations. Added sections 5.7 Loopback and 5.8 Exclusive AXI Accesses. Reworked
Chapter 6, Boot and Configuration
. Added section 7.2.4 Interrupt Sensitivity, Targeting
and Handling. Added sections 8.4.6 Clock Input Option for SWDT and 8.5.6 Clock Input
Option for Counter/Timer. Updated section 10.7 Register Overview. Added section
11.7 NOR Flash Bandwidth. Added sections AXI Read Command Processing and
12.2.7 Supported Memory Read and Write Commands. Added section 16.1.4 Clock
Domains and reworked section 16.7 Known Issues (previously titled “Limitations”.
Updated section 21.1.2 PL Resources by Device Type and added section 21.3.4 GTP
Low-Power Serial Transceivers. Added Peripheral Clock Gating subsection. Updated
Table 26-1 and Table 26-4. Updated register database in sections B.3 Module Summary
through B.34 USB Controller (usb) in Appendix B.
Date Version Revision
剩余1835页未读,继续阅读
资源评论
- whiteclouds2018-04-19好资料!支持!
- Law-Yao2018-05-07不错的参考手册~~
- mgc1232014-09-03很好,正在学习,谢谢
everybrightday
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