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JESD204C标准协议英文原文
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JESD204C标准协议英文原文
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JEDEC
STANDARD
Serial Interface for Data Converters
JESD204C.1
(Revision of JESD204C December 2017)
DECEMBER 2021
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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NOTICE
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through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC
legal counsel.
JEDEC standards and publications are designed to serve the public interest through eliminating
misunderstandings between manufacturers and purchasers, facilitating interchangeability and
improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the
proper product for use by those other than JEDEC members, whether the standard is to be used either
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JEDEC standards and publications are adopted without regard to whether or not their adoption may
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The information included in JEDEC standards and publications represents a sound approach to product
specification and application, principally from the solid state device manufacturer viewpoint. Within the
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No claims to be in conformance with this standard may be made unless all requirements stated in the
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This document is copyrighted by JEDEC and may not be
reproduced without permission.
For information, contact:
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Suite 240 South
Arlington, VA 22201-2107
or refer to www.jedec.org under Standards-Documents/Copyright Information.
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JEDEC Standard No. 204C.01
-i-
SERIAL INTERFACE FOR DATA CONVERTERS
CONTENTS
_Toc62286702
1 Scope ............................................................................................................................................................... 1
2 Normative references .................................................................................................................................... 3
3 Terminology ................................................................................................................................................... 4
3.1 Terms and definitions ................................................................................................................................... 4
3.2 Symbols and abbreviated terms ................................................................................................................... 9
4 Introduction and common requirements .................................................................................................. 16
4.1 Application overview ................................................................................................................................... 16
4.1.1 Background 16
4.1.2 Physical layer overview 17
4.1.3 Transport and link layer overview 18
Data encoding and organization .................................................................................................................... 18 4.1.3.1
Clocking ........................................................................................................................................................ 18 4.1.3.2
Sync header stream ........................................................................................................................................ 20 4.1.3.3
Deterministic latency ..................................................................................................................................... 20 4.1.3.4
4.1.4 Data link properties 20
Variants and modes ....................................................................................................................................... 21 4.1.4.1
4.1.5 Configuration examples 21
General .......................................................................................................................................................... 21 4.1.5.1
Single-device ADC application ..................................................................................................................... 21 4.1.5.2
Single-device DAC application ..................................................................................................................... 23 4.1.5.3
4.2 Deterministic latency ................................................................................................................................... 24
4.2.1 Introduction and general requirements 24
4.2.2 No support for deterministic latency (device subclass 0 and device subclass 1 using MULTIREF) 27
4.2.3 Deterministic latency using SYSREF (device subclass 1) 27
4.2.4 Deterministic latency using SYNC~ detection (device subclass 2) 27
4.3 Physical timing............................................................................................................................................. 28
4.3.1 Device clock 28
4.3.2 Link layer clock 29
4.3.3 Transport layer clock 29
4.3.4 Local multiframe and extended multiblock clocks (LMFC and LEMC) 30
4.3.5 SYSREF signal (device Subclass 1) 30
4.3.6 MULTIREF signal (device subclass 1) 32
4.3.7 SYNC~ generation and detection clocks (8B/10B link layer) 34
4.3.8 Skew and latency variation budget 35
4.4 Control interfaces ........................................................................................................................................ 46
4.5 Device classification ..................................................................................................................................... 46
4.5.1 Classes 46
4.5.2 Device subclassification 46
4.5.3 Features to be declared 47
5 Physical layer specification ......................................................................................................................... 48
5.1 Category B physical layer specification ..................................................................................................... 48
5.1.1 Electrical specification overview 48
5.1.2 Compliance types 49
5.1.3 Transmission medium 50
Transmission medium insertion loss ............................................................................................................. 51 5.1.3.1
5.1.4 Class B-3 (LV-OIF-SxI5) 51
Compliance ................................................................................................................................................... 51 5.1.4.1
Transmitter .................................................................................................................................................... 52 5.1.4.2
Receiver ......................................................................................................................................................... 53 5.1.4.3
5.1.5 Class B-6 (LV-OIF-6G-SR) 55
Compliance ................................................................................................................................................... 55 5.1.5.1
Transmitter .................................................................................................................................................... 56 5.1.5.2
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JEDEC Standard No. 204C.01
SERIAL INTERFACE FOR DATA CONVERTERS
CONTENTS (cont’d)
-ii-
Receiver ......................................................................................................................................................... 58 5.1.5.3
5.1.6 Class B-12 (LV-OIF-11G-SR) 59
Applicability above 11.1 Gbps ...................................................................................................................... 59 5.1.6.1
Compliance ................................................................................................................................................... 60 5.1.6.2
Transmitter .................................................................................................................................................... 61 5.1.6.3
Receiver ......................................................................................................................................................... 63 5.1.6.4
5.2 Category C physical layer specification..................................................................................................... 65
5.2.1 Overview 65
5.2.2 Compliance 65
Compliance types .......................................................................................................................................... 65 5.2.2.1
System compliance ........................................................................................................................................ 66 5.2.2.2
5.2.3 Transmitter characteristics 66
Transmitter electrical specifications .............................................................................................................. 66 5.2.3.1
Transmitter test fixture .................................................................................................................................. 68 5.2.3.2
Signaling rate and range ................................................................................................................................ 70 5.2.3.3
Signaling levels ............................................................................................................................................. 70 5.2.3.4
Transmitter transition (rise/fall) time ............................................................................................................ 71 5.2.3.5
Transmitter output return loss ....................................................................................................................... 72 5.2.3.6
Transmitter output waveform ........................................................................................................................ 73 5.2.3.7
Transmitter output noise and distortion ......................................................................................................... 76 5.2.3.8
Waveform acquisition ................................................................................................................................... 76 5.2.3.9
Test pattern .................................................................................................................................................... 77 5.2.3.10
Linear fit to the waveform measured at TP0a ............................................................................................... 77 5.2.3.11
Removal of the transfer function between the transmit function and TP0a................................................... 78 5.2.3.12
Transmitter output jitter................................................................................................................................. 78 5.2.3.13
5.2.3.13.1 Overview ................................................................................................................................................... 78
5.2.3.13.2 Even-odd jitter (DCD) ............................................................................................................................... 79
5.2.3.13.3 Effective bounded uncorrelated jitter (EBUJ) and effective random jitter (ERJ) ...................................... 79
5.2.4 Receiver characteristics 80
Receiver electrical specifications .................................................................................................................. 80 5.2.4.1
Receiver test fixture ...................................................................................................................................... 82 5.2.4.2
Signaling rate and range ................................................................................................................................ 84 5.2.4.3
Receiver input return loss .............................................................................................................................. 84 5.2.4.4
Receiver interference tolerance ..................................................................................................................... 86 5.2.4.5
5.2.4.5.1 Additive broadband noise characteristics ...................................................................................................... 88
Receiver jitter tolerance................................................................................................................................. 89 5.2.4.6
5.2.5 Channel characteristics 90
Insertion loss ................................................................................................................................................. 90 5.2.5.1
Isolation in package and footprint area.......................................................................................................... 91 5.2.5.2
Channel Operating Margin ............................................................................................................................ 93 5.2.5.3
Transmitter and receiver device package models .......................................................................................... 98 5.2.5.4
Filters............................................................................................................................................................. 98 5.2.5.5
5.2.5.5.1 Receiver noise filter ...................................................................................................................................... 99
5.2.5.5.2 Transmitter equalizer ..................................................................................................................................... 99
5.2.5.5.3 Receiver equalizer ......................................................................................................................................... 99
6 Transport layer .......................................................................................................................................... 100
6.1 Overview .................................................................................................................................................... 100
6.2 User data format for an independent lane .............................................................................................. 100
6.2.1 General 100
6.2.2 User data mapping without oversampling 101
6.2.3 User data mapping with oversampling 103
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