MCIMX6G0DVM05AA MCIMX6G0DVM05AB
MCIMX6G2DVM05AA MCIMX6G2DVM05AB
MCIMX6G3DVM05AA MCIMX6G3DVM05AB
MCIMX6G2DVK05AA MCIMX6G2DVK05AB
MCIMX6G3DVK05AA MCIMX6G3DVK05AB
Package Information
Plastic Package
BGA 14 x 14 mm, 0.8 mm pitch
BGA 9 x 9 mm, 0.5 mm pitch
Ordering Information
See Table 1 on page 3
NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6ULCEC
Rev. 2.2, 05/2017
© 2015-2017 NXP B.V.
1 i.MX 6UltraLite introduction
The i.MX 6UltraLite is a high performance, ultra
efficient processor family featuring NXP’s advanced
implementation of the single ARM Cortex
®
-A7 core,
which operates at speeds up to 528 MHz. The i.MX
6UltraLite includes an integrated power management
module that reduces the complexity of the external
power supply and simplifies the power sequencing. Each
processor in this family provides various memory
interfaces, including LPDDR2, DDR3, DDR3L, Raw
and Managed NAND flash, NOR flash, eMMC, Quad
SPI, and a wide range of other interfaces for connecting
peripherals, such as WLAN, Bluetooth™, GPS,
displays, and camera sensors.
The i.MX 6UltraLite is specifically useful for
applications such as:
• Electronics Point-of-Sale device
• Telematics
i.MX 6UltraLite
Applications Processors
for Consumer Products
1. i.MX 6UltraLite introduction . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Special signal considerations . . . . . . . . . . . . . . . 17
3.2. Recommended connections for unused analog
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 20
4.2. Power supplies requirements and restrictions . . . 28
4.3. Integrated LDO voltage regulator parameters . . . 29
4.4. PLL’s electrical characteristics . . . . . . . . . . . . . . . 31
4.5. On-Chip oscillators . . . . . . . . . . . . . . . . . . . . . . . 32
4.6. I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . 33
4.7. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . . 37
4.8. Output buffer impedance parameters . . . . . . . . . 40
4.9. System modules timing . . . . . . . . . . . . . . . . . . . . 43
4.10. Multi-Mode DDR Controller (MMDC) . . . . . . . . . . 53
4.12. External peripheral interface parameters . . . . . . 62
4.13. A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 95
5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 95
5.2. Boot device interface allocation . . . . . . . . . . . . . . 96
6. Package information and contact assignments . . . . . . 103
6.1. 14x14 mm package information . . . . . . . . . . . . 103
6.2. 9x9 mm package information . . . . . . . . . . . . . . 116
6.3. GPIO reset behaviors during reset . . . . . . . . . . 129
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
剩余131页未读，继续阅读
gushu114122
- 粉丝: 0
- 资源: 73
评论0