FIFO Generator v13.2 www.xilinx.com 4
PG057 October 4, 2017 Product Specification
Introduction
The Xilinx LogiCORE™ IP FIFO Generator core is
a fully verified first-in first-out (FIFO) memory
queue for applications requiring in-order
storage and retrieval. The core provides an
optimized solution for all FIFO configurations
and delivers maximum performance (up to 500
MHz) while utilizing minimum resources.
Delivered through the Vivado® Design Suite,
you can customize the width, depth, status
flags, memory type, and the write/read port
aspect ratios.
The FIFO Generator core supports Native
interface FIFOs, AXI Memory Mapped interface
FIFOs and AXI4-Stream interface FIFOs. Native
interface FIFO cores are optimized for
buffering, data width conversion and clock
domain decoupling applications, providing
ordered storage and retrieval.
AXI Memory Mapped and AXI4-Stream
interface FIFOs are derived from the Native
interface FIFO. Three AXI Memory Mapped
interface styles are available: AXI4, AXI3 and
AXI4-Lite.
For more details on the features of each
interface, see Feature Summary in Chapter 1.
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family
(1)
UltraScale+™ Families,
UltraScale™ Architecture, Zynq®-7000, 7 Series
Supported
User Interfaces
Native, AXI4-Stream, AXI4, AXI3, AXI4-Lite
Resources Performance and Resource Utilization web page
Provided with Core
Design Files Encrypted RTL
Example
Design
VHDL
Test Bench VHDL
Constraints
File
XDC
Simulation
Model
Verilog Behavioral
(2)
Supported
S/W Driver
N/A
Tested Design Fl ows
(4)
Design Entry Vivado Design Suite
Simulation
(3)
For other supported simulators, see the Xilinx
Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete listing of supported devices, see the Vivado IP
catalog.
2. Behavioral model does not model synchronization delay.
See
Simulation in Chapter 4 for details.
3. The FIFO Generator core supports the UniSim simulation
model.
4. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
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