Altera官方的FIFO使用指导

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ALTERA官方给出的FIFO使用说明,在LPM库中提供了参数可配置的单时钟FIFO(SCFIFO)和双时钟FIFO(DCFIFO)。
UG-MFNALT FIFO 2015.11.02 SCFIFO and DCFIFO Signals igure 1: SCFIFO and DCFIFO IP Cores Input and Output Signals S〔FF0 DCFIFO datal7. 0 data[7.0 wrfull wrre empty almost full burck wrusedw[8.0 empt q[7.0] almost empt Srdclk usedw[7.0 empty eccstatus[1: 0 rdusedw[8.0 ac eccstatus[ 1: 0] For the SCFifo block, the read and write signals are synchronized to the same clock; for the dcfifo block, the read and write signals are synchronized to the and clocks respectively. The prefixes and represent the signals that are synchronized by the and clocks respectively Table 2: Input and output Ports Description This table lists the signals of the IP cores. The term series"refers to all the device families of a particular device For example, Stratix series refers to the Stratix Iv and stratix V, unless specified otherwise Port Type Required Description Input Y es Positive-edge-triggered clock Input Yes Positive-edge-triggered clock Use to synchronize the following ports Input Yes po oSitive-edge-triggered cloCk Use to synchronize the following ports (1) Only applicable for the SCFIFO IP core (2)Applicable for both of the DCFIFo IP cores SCFIFO and dCfiFo iP Cores user guide Altera Corporation Send Feedback UG-MFNALT FIFO SCFIFO and DCFIFO Signals 2015.11.02 Port Type Required Description Input Yes Holds the data to be written in the fifo ip core when the signal is asserted. If you manually instantiate the FIFO IP core, ensure the port width is equal to the parameter. (3) Input Yes Assert this signal to request for a write operation Ensure that the following conditions are met ● Do not assert the signal when the (for SCFIFOor (for DCFiFO) port is high enable the overflow protection circuitry or set the can auton parameter to on so that the FIFO IP core hatically disable the signal when it is full The signal must meet the functional timing requirement based on the or Signa Do not assert the signal during the deassertion of the signal. Violating this requirement creates a race condition between the falling edge of the signal and the rising edge of the write clock if the port is set to high. For both the dCFIFo IP ores that target stratix and Cyclone series, you have the option to automatically add a circuit to synchronize the signal with the clock. or set the parameter to ON. Use this option to ensure that the restriction is obeyed Input Yes Assert this signal to request for a read operation The signal acts differently in normal mode and show head mode Ensure that the following conditions are met Do not assert the signal when the r SCFIFO)or (for DCFIFO) port is high Enable the underflow protection circuitry or set the parameter to on so that the FIFO IP core can automatically disable the signal when it is empty The signal must meet the functional timin requirement based on the signal. Input Assert this signal to clear all the output status ports, but the effect on the output may vary for different Fifo configurations There are no minimum number of clock cycles for signals that must remain active (3)Applicable for the SCFIFO, DCFIFO, and DCFIFO_MIXED_WIDTH IP cores Altera Corporation SCFIFO and dCfIFo IP Cores User Guide □ Send Feedback UG-MFNALT FIFO 2015.11.02 SCFIFO and DCFIFO Signals Port Type Required Description Output Yes Shows the data read from the read request operation For the sCFifo ip core and dcfifo ip core, the width of the port must be equal to the width of the port If you manually instantiate the IP cores, ensure that the port width is equal to the parameter. For the DCFiFo MIXED WIDths IP core, the width of the port can be different from the width of the port. If you manually instantiate the IP core, ensure that the width of the equal to the Parameter. The IP core supports a wide write port with a narrow read port, and vice versa. However, the width ratio is restricted by the type of ram block, and in general, are in the power of 2 Output No When asserted the Fifo iP core is considered full. Do not perform write request operation when the FIFO IP core is full (2)(4 general, the signal is a delayed version of the signal. However, for Stratix IiI devices and later, signal function as a combinational output instead of a derived version of the signal Therefore, you must always refer to the port to ensure whether or not a valid write request operation can be performed, regardless of the target device Output No When asserted, the FiFo IP core is considered empty. Do (2)(4) not perform read request operation when the FIFO IP core is empt (2)(4) In general, the signal is a delayed version of the signal. However, for Stratix Ill devices and later, ne signal function as a combinational output instead of a derived version of the signal. Therefore, you must always refer to the ort to ensure whether or not a valid read request operation can be performed, regardless of the target device (1) Output N asserted when the signal is greater than or equal to the parameter. It is used as an early indication of the Signa Output Asserted when the signal is less than the parameter. It is used as an early indication of the sigr (1) Only applicable for the DCFIFO_MIXED_WIDTHS IP core SCFIFO and dCfiFo iP Cores user guide Altera Corporation Send Feedback UG-MFNALT FIFO SCFIFO and DCFIFO Signals 2015.11.02 Port Type Required Description Output No Show the number of words stored in the fifo (2)(4) Ensure that the port width is equal to the (2)(4) parameter if you manually instantiate the SCFIfO IP core or the dcfifo ip core for the dcfifo miXed WIDTH IP core, the width of the ports must be equal to the an parameters respectively For Stratix, Stratix GX, and Cyclone devices the FIfo ip core shows full even before the number of words stored reaches its maximum value. Therefore, you must always refer to the or port for valid write request operation, and the or port for valid read request operation regardless of the target device (5) Outp A 2-bit wide error correction status port Indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit occurs Noerror Illegal A correctable error occurred and the error has been corrected at the outputs; however, the memory array has not been updated An uncorrectable error occurred and uncorrectable data appears at the output This port is only available for Arria 10 devices using M20K memory block type and with 32-bit FIFO width The dcFifo ip core output may momentarily glitch when the input is asserted. To prevent an external register from capturing this glitch incorrectly, ensure that one of the following is true The external register must use the same reset which is connected to the input of the dCFifo Ip core or The reset connected to the input of the DCFIFO IP core must be asserted synchronous to the clock which drives the external register The output latency information of the FIFO IP cores is important, especially for the output port, because there is no output flag to indicate when the output is valid to be sampled (5) Not applicable for the DCFIFo_MIXED_WIDTHS IP core Altera Corporation SCFIFO and dCfIFo IP Cores User Guide □ Send Feedback UG-MFNALT FIFO 2015.11.02 SCFIFO and dcfifo parameters SCFIFO and dcfifo parameters Table 3: SCFIFo and dcfifo parameters Parameter Type Required Description Integer Yes Specifies the width of the and ports for the SCFIFO IP core and DCFiFo IP core For the DCFIFO MIXED WIDTHS IP core. this parameter specifies only the width of the Integer Yes Specifies the width of the port for the DCFIFo MIXED WIDTHS IP core Integer Yes Specifies the width of the port for the SCFIFO IP core, or the width of the and ports for the dCFiFo IP core. For the DCFIFO MIXED WIDTHS IP core, it only represents the width of the port. Integer Yes Specifies the width of the port for the DCFIFO MIXED WIDTHS IP core Integer es Specifies the depths of the FifO you require. The value must be at least 4 The value assigned must comply to the following equation 2ALPM WIDTHU Strins Yes ecifies whether the fifo is in normal mode or show-ahead mode( ) SCFIFO and DCFIFO Show- Ahead mode If you set the parameter to ON, you may reduce performance. String Identifies the library of parameterized modules LPM entity name. The values are SCFIFo and DCFIFO String Specifies whether or not to enable the protection circuitry for overflow checking that disables the port when the FIfO IP core is full. The values are on or off. if omitted the default is ON (6) Only applicable for the DCFIFO_MIXED_WIDTHS IP core SCFIFO and dCfiFo iP Cores user guide Altera Corporation Send Feedback UG-MFNALT FIFO SCFIFO and dCfiFo Parameters 2015.11.02 Parameter Type Required Description Strin g Specifies whether or not to enable the protection circuitry for underflow checking that disables the port when the fifo ip core is empty The values are on or off. if omitted the default is ON Note that reading from an empty SCFIFO gives unpredictable results String No Specifies whether to enable the ecc feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory. This option is only available for Arria 10 devices using M20K memory block type and with 32-bit FIFO width The ecc is disabled by default Strin Specify the number of register slages that you want to internally add to the ort using the respective parameter The default value of adds a single register stage to the output to improve its performance Increasing the value of the parameter does not increase the maximum system speed It only adds additional latency to the respective output port Integer No Specify the number of synchronization stages in the cross clock domain. The value of the parameter relates the synchronization stages from the write control logic to the read control logic, the parameter relates the synchronization stages from the read control logic to the write control logic. Use these parameters to set the number of synchronization stages if the clocks are not synchronized, and set the parameter to FALSE The actual synchronization stage implemented relates variously to the parameter value assigned, depends on the target de The values of these parameters are internally reduced by two. Thus, the default value of 3 for these parameters corresponds lo a single synchro nization stage, a value of 4 results in two synchro nization stages, and so on. Choose at least 4(two synchronization stages) for metastability orotection (7 Not applicable for the DCFIFO_ MIXED_WIDTHS IP core (S) Only applicable for the DCFIFO IP core Altera Corporation SCFIFO and dCfIFo IP Cores User Guide □ Send Feedback UG-MFNALT FIFO 2015.11.02 SCFIFO and dCfifo parameters Parameter Type Required Description Strin g Specifies whether or not the FIFO IP core is constructed using the RAM blocks. The values are on or OFF Setting this parameter value to OFF yields the FIFO IP core in nted in logic elements regardless of the type of the TriMatrix memory block type assigned to the This parameter is enabled by default FIFo will be implemented using Ram blocks specified in ram block_ type String Specifies whether or not to add a circuit that causes the port to be internally synchronized by the lock. Adding the circuit prevents the dition be that could corrupt the Fifo ip core The values are on or off. if omitted the default value is OFF. This parameter is only applicable for Stratix and Cyclone series String Specifies whether or not to add a circuit that causes the port to be internally synchronized clock. Adding the circuit prevents the race condition between the and orts Chat could corrupt the FIfo ip core The values are on or off. if omitted the default value is ofF (8) String Specifies whether or not the write and read clocks are synchronized which in turn determines the number of internal synchronization stages added for stable operation of the FIFo. The values are TRUE and False if omitted the default value is FALSE. You must only set the parameter to TRuE if the write clock and the read clock are always synchronized and they are multiples of each othe Otherwise, set this to FALSE to avoid metastability problems If the clocks are not synch yI ronized set the parameter to FALSE, and use the nd arameters lo determine the number of synchronization stages required SCFIFO and dCfiFo iP Cores user guide Altera Corporation Send Feedback UG-MFNALT FIFO 10 SCFIFO and DCFIFO Functional Timing requirements 2015.11.02 Parameter Type Required Description Strin g Specifies the target device's Trimatrix Memory Block to be used. To get the proper implementa tion based on the ram configuration that you set, allow the quartus prime software to automatically choose the memory type by ignoring this parameter and set the a、 Parameter to ON This gives the compiler the flexibility to place the memory function in any available memory resource based on the Fifo depth required. Types of RAM block type available; MLAB, M20K and M144K Strin Specifies whether to register the output. The values are on and off. if omitted the default value is off You can set the parameter to on or off for the SCFIFO or the dcfifo, that do not target Stratix II, Cyclone Il, and new devices. This parameter does not apply to these devices because the output must be registered in normal mode nd unregistered in show-ahead mode for the DCFIFO Integer Sets the threshold value for the port. When the number of words stored in the fifo ip core is greater than or equal to this value, th port is asserted Integer No Sets the threshold value for the port. When the number of words stored in the FIFO IP core is less than this value. the rt is asserted String g Allows you lo combine read and write cycles to an already full sCFifo, so that it remains full. The values are on and off. if omitted the default is OFF. Use only this parameter when the parameter is set to ON String Specifies the intended device that matches the device set in your Quartus Prime project. USe only this parameter for functional simulation SCFIFO and dCFiFo Functional Timing Requirements The signal is ignored(when FIFO is full) if you enable the overflow protection circuitry in the FIFO parameter editor, or set the parameter to signal is ignored(when FIFO is empty) if you enable the underflow protection circuitry in the FIFO IP core interlace, or set the parameter to (9) Only applicable for the SCFIFO IP core Altera Corporation SCFIFO and dCfIFo IP Cores User Guide □ Send Feedback

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