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ARM Neon指令的介绍
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ARM Neon指令的介绍
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Arm Neon Intrinsics
Reference for ACLE Q3 2020
Non-Confidential
Issue G
Copyright © 2014 - 2020 Arm Limited (or its affiliates).
All rights reserved.
IHI 0073G
Arm Neon Intrinsics Reference
IHI 0073G
Copyright © 2014 - 2020 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 2 of 185
Arm Neon Intrinsics
Reference
Copyright
©
2014 - 2020 Arm Limited (or its affiliates). All rights reserved.
Release information
Document history
Issue
Date
Confidentiality
Change
A
09 May 2014
Non-Confidential
First release
B
24 March
2016
Non-Confidential
Updated for ARMv8.1
C
30 March
2019
Non-Confidential
Version ACLE Q1 2019.
D
30 June 2019
Non-Confidential
Version ACLE Q2 2019.
E
30 September
2019
Non-Confidential
Version ACLE Q3 2019
F
30 May 2020
Non-Confidential
Version ACLE Q2 2020
G
30 October
2020
Non-Confidential
Version ACLE Q3 2020
Non-Confidential Proprietary Notice
This document is protected by copyright and other related rights and the practice or implementation
of the information contained in this document may be protected by one or more patents or pending
patent applications. No part of this document may be reproduced in any form by any means without
the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise
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DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL,
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Arm Neon Intrinsics Reference
IHI 0073G
Copyright © 2014 - 2020 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 3 of 185
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Copyright
©
2014 - 2020 Arm Limited (or its affiliates). All rights reserved.
Arm Limited. Company 02557590 registered in England.
110 Fulbourn Road, Cambridge, England CB1 9NJ.
LES-PRE-20349
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject
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Web Address
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Arm Neon Intrinsics Reference
IHI 0073G
Copyright © 2014 - 2020 Arm Limited (or its affiliates). All rights reserved.
Non-Confidential
Page 5 of 185
List of Intrinsics
Intrinsic
Argument
Preparation
Instruction
Result
Supported
Architectures
int8x8_t vadd_s8(int8x8_t a, int8x8_t b)
a -> Vn.8B
b -> Vm.8B
ADD Vd.8B,Vn.8B,Vm.8B
Vd.8B -> result
v7/A32/A64
int8x16_t vaddq_s8(int8x16_t a, int8x16_t b)
a -> Vn.16B
b -> Vm.16B
ADD Vd.16B,Vn.16B,Vm.16B
Vd.16B ->
result
v7/A32/A64
int16x4_t vadd_s16(int16x4_t a, int16x4_t b)
a -> Vn.4H
b -> Vm.4H
ADD Vd.4H,Vn.4H,Vm.4H
Vd.4H -> result
v7/A32/A64
int16x8_t vaddq_s16(int16x8_t a, int16x8_t b)
a -> Vn.8H
b -> Vm.8H
ADD Vd.8H,Vn.8H,Vm.8H
Vd.8H -> result
v7/A32/A64
int32x2_t vadd_s32(int32x2_t a, int32x2_t b)
a -> Vn.2S
b -> Vm.2S
ADD Vd.2S,Vn.2S,Vm.2S
Vd.2S -> result
v7/A32/A64
int32x4_t vaddq_s32(int32x4_t a, int32x4_t b)
a -> Vn.4S
b -> Vm.4S
ADD Vd.4S,Vn.4S,Vm.4S
Vd.4S -> result
v7/A32/A64
int64x1_t vadd_s64(int64x1_t a, int64x1_t b)
a -> Dn
b -> Dm
ADD Dd,Dn,Dm
Dd -> result
v7/A32/A64
int64x2_t vaddq_s64(int64x2_t a, int64x2_t b)
a -> Vn.2D
b -> Vm.2D
ADD Vd.2D,Vn.2D,Vm.2D
Vd.2D -> result
v7/A32/A64
uint8x8_t vadd_u8(uint8x8_t a, uint8x8_t b)
a -> Vn.8B
b -> Vm.8B
ADD Vd.8B,Vn.8B,Vm.8B
Vd.8B -> result
v7/A32/A64
uint8x16_t vaddq_u8(uint8x16_t a, uint8x16_t b)
a -> Vn.16B
b -> Vm.16B
ADD Vd.16B,Vn.16B,Vm.16B
Vd.16B ->
result
v7/A32/A64
uint16x4_t vadd_u16(uint16x4_t a, uint16x4_t b)
a -> Vn.4H
b -> Vm.4H
ADD Vd.4H,Vn.4H,Vm.4H
Vd.4H -> result
v7/A32/A64
uint16x8_t vaddq_u16(uint16x8_t a, uint16x8_t b)
a -> Vn.8H
b -> Vm.8H
ADD Vd.8H,Vn.8H,Vm.8H
Vd.8H -> result
v7/A32/A64
uint32x2_t vadd_u32(uint32x2_t a, uint32x2_t b)
a -> Vn.2S
b -> Vm.2S
ADD Vd.2S,Vn.2S,Vm.2S
Vd.2S -> result
v7/A32/A64
uint32x4_t vaddq_u32(uint32x4_t a, uint32x4_t b)
a -> Vn.4S
b -> Vm.4S
ADD Vd.4S,Vn.4S,Vm.4S
Vd.4S -> result
v7/A32/A64
uint64x1_t vadd_u64(uint64x1_t a, uint64x1_t b)
a -> Dn
b -> Dm
ADD Dd,Dn,Dm
Dd -> result
v7/A32/A64
uint64x2_t vaddq_u64(uint64x2_t a, uint64x2_t b)
a -> Vn.2D
b -> Vm.2D
ADD Vd.2D,Vn.2D,Vm.2D
Vd.2D -> result
v7/A32/A64
float32x2_t vadd_f32(float32x2_t a, float32x2_t b)
a -> Vn.2S
b -> Vm.2S
FADD Vd.2S,Vn.2S,Vm.2S
Vd.2S -> result
v7/A32/A64
float32x4_t vaddq_f32(float32x4_t a, float32x4_t b)
a -> Vn.4S
b -> Vm.4S
FADD Vd.4S,Vn.4S,Vm.4S
Vd.4S -> result
v7/A32/A64
float64x1_t vadd_f64(float64x1_t a, float64x1_t b)
a -> Dn
b -> Dm
FADD Dd,Dn,Dm
Dd -> result
A64
float64x2_t vaddq_f64(float64x2_t a, float64x2_t b)
a -> Vn.2D
b -> Vm.2D
FADD Vd.2D,Vn.2D,Vm.2D
Vd.2D -> result
A64
int64_t vaddd_s64(int64_t a, int64_t b)
a -> Dn
b -> Dm
ADD Dd,Dn,Dm
Dd -> result
A64
uint64_t vaddd_u64(uint64_t a, uint64_t b)
a -> Dn
b -> Dm
ADD Dd,Dn,Dm
Dd -> result
A64
int16x8_t vaddl_s8(int8x8_t a, int8x8_t b)
a -> Vn.8B
b -> Vm.8B
SADDL Vd.8H,Vn.8B,Vm.8B
Vd.8H -> result
v7/A32/A64
int32x4_t vaddl_s16(int16x4_t a, int16x4_t b)
a -> Vn.4H
b -> Vm.4H
SADDL Vd.4S,Vn.4H,Vm.4H
Vd.4S -> result
v7/A32/A64
int64x2_t vaddl_s32(int32x2_t a, int32x2_t b)
a -> Vn.2S
b -> Vm.2S
SADDL Vd.2D,Vn.2S,Vm.2S
Vd.2D -> result
v7/A32/A64
uint16x8_t vaddl_u8(uint8x8_t a, uint8x8_t b)
a -> Vn.8B
b -> Vm.8B
UADDL Vd.8H,Vn.8B,Vm.8B
Vd.8H -> result
v7/A32/A64
uint32x4_t vaddl_u16(uint16x4_t a, uint16x4_t b)
a -> Vn.4H
b -> Vm.4H
UADDL Vd.4S,Vn.4H,Vm.4H
Vd.4S -> result
v7/A32/A64
uint64x2_t vaddl_u32(uint32x2_t a, uint32x2_t b)
a -> Vn.2S
b -> Vm.2S
UADDL Vd.2D,Vn.2S,Vm.2S
Vd.2D -> result
v7/A32/A64
int16x8_t vaddl_high_s8(int8x16_t a, int8x16_t b)
a -> Vn.16B
b -> Vm.16B
SADDL2 Vd.8H,Vn.16B,Vm.16B
Vd.8H -> result
A64
int32x4_t vaddl_high_s16(int16x8_t a, int16x8_t b)
a -> Vn.8H
b -> Vm.8H
SADDL2 Vd.4S,Vn.8H,Vm.8H
Vd.4S -> result
A64
int64x2_t vaddl_high_s32(int32x4_t a, int32x4_t b)
a -> Vn.4S
b -> Vm.4S
SADDL2 Vd.2D,Vn.4S,Vm.4S
Vd.2D -> result
A64
uint16x8_t vaddl_high_u8(uint8x16_t a, uint8x16_t b)
a -> Vn.16B
b -> Vm.16B
UADDL2 Vd.8H,Vn.16B,Vm.16B
Vd.8H -> result
A64
uint32x4_t vaddl_high_u16(uint16x8_t a, uint16x8_t
b)
a -> Vn.8H
b -> Vm.8H
UADDL2 Vd.4S,Vn.8H,Vm.8H
Vd.4S -> result
A64
uint64x2_t vaddl_high_u32(uint32x4_t a, uint32x4_t
b)
a -> Vn.4S
b -> Vm.4S
UADDL2 Vd.2D,Vn.4S,Vm.4S
Vd.2D -> result
A64
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