INTRODUCTION TO SIMULATION OF VHDL DESIGNS For Quartus II 13.0
The Simulation Waveform Editor is available for use with Altera’s Quartus II software version 13.0 or later. It al-
lows the user to apply inputs to the designed circuit, usually referred to as test vectors, and to observe the outputs
generated in response.
In this tutorial, the reader will learn about:
• Test vectors needed to test the designed circuit
• Using the Simulation Waveform Editor to draw test vectors
• Functional simulation, which is used to verify the functional correctness of a synthesized circuit
• Timing simulation, which is used to verify the timing of signals in a synthesized circuit
This tutorial is aimed at the reader who wishes to simulate circuits defined by using the VHDL hardware description
language. An equivalent tutorial is available for the user who prefers the Verilog language.
2 Design Project
To illustrate the simulation process, we will use a very simple logic circuit that implements the majority3 function
of three inputs, x
1
, x
2
and x
3
. The circuit is defined by the expression
f (x
1
, x
2
, x
3
) = x
1
x
2
+ x
1
x
3
+ x
2
x
3
In VHDL, this circuit can be specified as follows:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY majority3 IS
PORT(
x1, x2, x3 : IN STD_LOGIC;
f : OUT STD_LOGIC);
END majority3;
ARCHITECTURE majority3_rtl OF majority3 IS
BEGIN
f <= (x1 AND x2) OR (x1 AND x3) OR (x2 AND x3);
END majority3_rtl;
Enter this code into a file called majority3.vhd.
The desired circuit has to be first implemented in a Quartus II project. To do so, create a new directory (folder) for
the Quartus II project, and for consistence with the description in this tutorial call it simulator_intro. Copy the file
majority3.vhd into this directory. Then, create a Quartus II project and call it majority3. Compile your design.
2 Altera Corporation - University Program
February 2013
