AT91系列微处理器复位电路应该注意的问题.pdf

NRST is an active low-level input. It is asserted asynchronously but exit from the reset is

synchronized internally to the MCK. The signal presented on MCK must be active within

ensure correct operation.

The watchdog can be programmed to generate an internal reset. In this case, the reset

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maxi-

fetch from address zero. Except for the program counter, the ARM7TDMI registers do

not have defined reset states. When reset is active, the inputs of the AT91 microcontrol-

drive low during reset.

enables the connection of an emulator probe to an application board without having to

desolder the device from the target board. In tri-state mode, all the output pin drivers of

the AT91X40 series microcontroller are disabled. To enter tri-state mode, the pin NTRI

must be held low during the last 10 clock cycles before the rising edge of NRST. For

normal operation, the pin NTRI must be held high during reset by a resistor of up to

mapped to non volatile memory after the reset.

the NRST selects the type of boot memory. The boot mode depends on the device and

microcontroller family uses a remap command that enables switching between the boot

memory and the internal SRAM bank addresses. The remap command is accessible via

the EBI user interface. The remap operation can be changed back only by an internal

Table 2. Boot Mode Select

• 8-bit or 16-bit data bus width, depending on BMS (refer to Table 1)

The EBI provides two alternative protocols for external memory read access: standard

and early read. Standard read protocol is the default protocol after reset.