RTL8370MB
LAYER 2 MANAGED 8+2-PORT 10/100/1000
SWITCH CONTROLLER
DRAFT DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 0.2
Aug 11, 2015
Track ID:
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
Provider：HK NATER TECH LIMITED
Add： 2F,NO.27,2 Baomin Rd.,Baoan Dist.SZ City,China
Tel：+86-755-85250145/13510620050
Fax：+86-755-61522172
Attn：Lingo
E-mail：hsdgood@163.com
i
COPYRIGHT
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means without the written permission of Realtek Semiconductor Corp.
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could include technical inaccuracies or typographical errors.
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USING THIS DOCUMENT
This document is intended for the hardware and software engineer‟s general information on the Realtek
RTL8370MB IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
Release Date
Summary
0.1
2015-05-26
First release.
0.2
2015-08-11
Revise some description and error.
Add chapter 10.5.2 SPI FLASH Interface Timing Characteristics,10.5.13~10.5.16
SGMII/1000Base-X/100FX Interface Timing Characteristics
RTL8370MB
DRAFT Datasheet
Layer-2 Managed 8+2-Port 10/100/1000 Switch Controllers
ii
Track ID: Rev. 0.2
Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2. FEATURES ......................................................................................................................................................................... 3
3. BLOCK DIAGRAM ........................................................................................................................................................... 5
4. SYSTEM APPLICATION ................................................................................................................................................. 6
4.1. 8-PORT 1000BASE-T+2-PORT 1000BASE-X/100BASE-FX SWITCH ............................................................................ 6
4.2. 8-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII............................................................................................... 7
4.3. 8-PORT 1000BASE-T ROUTER WITH DUAL SGMII ...................................................................................................... 8
5. PIN ASSIGNMENTS ......................................................................................................................................................... 9
5.1. PACKAGE IDENTIFICATION ........................................................................................................................................... 9
5.2. PIN ASSIGNMENT TABLE ............................................................................................................................................ 10
6. PIN DESCRIPTIONS ...................................................................................................................................................... 13
6.1. MEDIA DEPENDENT INTERFACE PINS ......................................................................................................................... 13
6.2. RGMII INTERFACE PINS ............................................................................................................................................ 14
6.3. MII/TMII INTERFACE PINS ........................................................................................................................................ 15
6.4. RMII INTERFACE PINS ............................................................................................................................................... 17
6.5. SERDES INTERFACE PINS ........................................................................................................................................... 18
6.6. PARALLEL LED PINS ................................................................................................................................................. 18
6.7. SERIAL MODE LED PINS............................................................................................................................................ 20
6.8. SPI FLASH INTERFACE PINS ..................................................................................................................................... 20
6.9. UART INTERFACE PINS ............................................................................................................................................. 20
6.10. CPU INTERFACE PINS ................................................................................................................................................ 21
6.11. GPIO INTERFACE PINS ............................................................................................................................................... 21
6.12. CONFIGURATION STRAPPING PINS ............................................................................................................................. 22
6.13. MISCELLANEOUS PINS ............................................................................................................................................... 24
6.14. TEST PINS .................................................................................................................................................................. 25
6.15. POWER AND GND PINS .............................................................................................................................................. 26
7. PHYSICAL LAYER FUNCTIONAL OVERVIEW...................................................................................................... 27
7.1. MDI INTERFACE ........................................................................................................................................................ 27
7.2. 1000BASE-T TRANSMIT FUNCTION ........................................................................................................................... 27
7.3. 1000BASE-T RECEIVE FUNCTION .............................................................................................................................. 27
7.4. 100BASE-TX TRANSMIT FUNCTION ........................................................................................................................... 27
7.5. 100BASE-TX RECEIVE FUNCTION ............................................................................................................................. 27
7.6. 10BASE-T TRANSMIT FUNCTION ............................................................................................................................... 28
7.7. 10BASE-T RECEIVE FUNCTION .................................................................................................................................. 28
7.8. AUTO-NEGOTIATION FOR UTP .................................................................................................................................. 28
7.9. CROSSOVER DETECTION AND AUTO CORRECTION ..................................................................................................... 28
7.10. POLARITY CORRECTION ............................................................................................................................................. 28
8. GENERAL FUNCTION DESCRIPTION ...................................................................................................................... 30
8.1. RESET ........................................................................................................................................................................ 30
8.1.1. Hardware Reset .................................................................................................................................................... 30
8.1.2. Software Reset ...................................................................................................................................................... 30
8.2. IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................ 30
8.3. HALF DUPLEX FLOW CONTROL ................................................................................................................................. 31
8.3.1. Back-Pressure Mode ............................................................................................................................................ 31
8.4. SEARCH AND LEARNING ............................................................................................................................................ 31
8.5. SVL AND IVL/SVL ................................................................................................................................................... 32
8.6. ILLEGAL FRAME FILTERING ....................................................................................................................................... 32
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DRAFT Datasheet
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8.7. IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL ............................................................................. 32
8.8. BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL ..................................................................................... 33
8.9. PORT SECURITY FUNCTION ........................................................................................................................................ 33
8.10. MIB COUNTERS ......................................................................................................................................................... 33
8.11. PORT MIRRORING ...................................................................................................................................................... 33
8.12. VLAN FUNCTION ...................................................................................................................................................... 33
8.12.1. Port-Based VLAN ............................................................................................................................................ 34
8.12.2. IEEE 802.1Q Tag-Based VLAN ....................................................................................................................... 34
8.12.3. Protocol-Based VLAN ..................................................................................................................................... 35
8.12.4. Port VID .......................................................................................................................................................... 35
8.13. QOS FUNCTION .......................................................................................................................................................... 35
8.13.1. Input Bandwidth Control ................................................................................................................................. 36
8.13.2. Priority Assignment ......................................................................................................................................... 36
8.13.3. Priority Queue Scheduling............................................................................................................................... 36
8.13.4. IEEE 802.1p/Q and DSCP Remarking ............................................................................................................ 37
8.13.5. ACL-Based Priority ......................................................................................................................................... 37
8.14. IGMP & MLD SNOOPING FUNCTION ......................................................................................................................... 37
8.15. IEEE 802.1X FUNCTION ............................................................................................................................................. 37
8.15.1. Port-Based Access Control .............................................................................................................................. 37
8.15.2. Authorized Port-Based Access Control ........................................................................................................... 38
8.15.3. Port-Based Access Control Direction .............................................................................................................. 38
8.15.4. MAC-Based Access Control............................................................................................................................. 38
8.15.5. MAC-Based Access Control Direction ............................................................................................................ 38
8.15.6. Optional Unauthorized Behavior ..................................................................................................................... 38
8.15.7. Guest VLAN ..................................................................................................................................................... 38
8.16. IIEEE 802.1D FUNCTION ........................................................................................................................................... 38
8.17. EMBEDDED 8051 ........................................................................................................................................................ 39
8.18. REALTEK CABLE TEST (RTCT) ................................................................................................................................. 39
8.19. LED INDICATOR ........................................................................................................................................................ 39
8.19.1. Parallel LED Mode.......................................................................................................................................... 40
8.19.2. Serial LED Mode ............................................................................................................................................. 41
8.20. GREEN ETHERNET ...................................................................................................................................................... 44
8.20.1. Link-On and Cable Length Power Saving ....................................................................................................... 44
8.20.2. Link-Down Power Saving ................................................................................................................................ 44
8.21. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ............................................................................... 44
8.22. INTERRUPT PIN FOR EXTERNAL CPU ......................................................................................................................... 45
9. INTERFACE DESCRIPTIONS ...................................................................................................................................... 46
9.1. I
2
C MASTER FOR EEPROM AUTO-LOAD ................................................................................................................... 46
9.2. I
2
C-LIKE SLAVE INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8370MB ............................................................ 47
9.3. SLAVE MII MANAGEMENT SMI INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8370MB .................................... 48
9.4. SLAVE SPI INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8370MB ..................................................................... 48
9.5. SPI FLASH INTERFACE ............................................................................................................................................. 49
9.6. EXTENSION GMAC1 & GMAC2 RGMII/MII/TMII/RMII INTERFACE ..................................................................... 49
9.6.1. Extension GMAC1 and GMAC2 RGMII Mode..................................................................................................... 50
9.6.2. Extension GMAC1 and GMAC2 Full Duplex MII MAC/PHY Mode Interface .................................................... 53
9.6.3. Extension GMAC1 and GMAC2 Full Duplex TMII MAC/PHY Mode Interface .................................................. 57
9.6.4. Extension GMAC1 and GMAC2 RMII MAC/PHY Mode Interface ...................................................................... 61
9.7. EXTENSION GMAC1 & GMAC2 SGMII/1000BASE-X/100BASE-FX INTERFACE..................................................... 65
9.7.1. Extension GMAC1 and GMAC2 SGMII Interface ................................................................................................ 65
9.7.2. Extension GMAC1 and GMAC2 1000Base-X/100Base-FX Interface .................................................................. 66
10. ELECTRICAL CHARACTERISTICS .......................................................................................................................... 67
10.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 67
10.2. RECOMMENDED OPERATING RANGE .......................................................................................................................... 67
10.3. THERMAL CHARACTERISTICS .................................................................................................................................... 67
10.3.1. TQFP-176-EPAD ............................................................................................................................................ 67
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Track ID: Rev. 0.2
10.4. DC CHARACTERISTICS ............................................................................................................................................... 69
10.5. AC CHARACTERISTICS ............................................................................................................................................... 71
10.5.1. I
2
C Master for EEPROM Auto-load Interface Timing Characteristics ........................................................... 71
10.5.2. SPI FLASH Interface Timing Characteristics ................................................................................................. 72
10.5.3. I
2
C-Like Slave Mode for External CPU Access Interface Timing Characteristics .......................................... 73
10.5.4. Slave MII Management SMI for External CPU Access Interface Timing Characteristics .............................. 73
10.5.5. Slave SPI for External CPU Access Interface Timing Characteristics ............................................................ 75
10.5.6. RGMII Timing Characteristics ........................................................................................................................ 76
10.5.7. MII MAC Mode Timing ................................................................................................................................... 78
10.5.8. MII PHY Mode Timing .................................................................................................................................... 79
10.5.9. TMII MAC Mode Timing ................................................................................................................................. 80
10.5.10. TMII PHY Mode Timing .................................................................................................................................. 81
10.5.11. RMII MAC Mode Timing ................................................................................................................................. 82
10.5.12. RMII PHY Mode Timing .................................................................................................................................. 83
10.5.13. SGMII Differential Transmitter Characteristics.............................................................................................. 84
10.5.14. SGMII Differential Receiver Characteristics .................................................................................................. 85
10.5.15. 1000Base-X/100Base-FX Differential Transmitter Characteristics ................................................................ 86
10.5.16. 1000Base-X/100Base-FX Differential Receiver Characteristics ..................................................................... 87
10.6. POWER AND RESET CHARACTERISTICS ...................................................................................................................... 88
11. MECHANICAL DIMENSIONS...................................................................................................................................... 89
12. ORDERING INFORMATION ........................................................................................................................................ 90
List of Tables
TABLE 1. PIN ASSIGNMENT TABLE ............................................................................................................................................... 10
TABLE 2. MEDIA DEPENDENT INTERFACE PINS............................................................................................................................. 13
TABLE 3. RGMII INTERFACE PINS ................................................................................................................................................ 14
TABLE 4. MII/TMII INTERFACE PINS ............................................................................................................................................ 15
TABLE 5. RMII INTERFACE PINS ................................................................................................................................................... 17
TABLE 6. SERDES INTERFACE PINS ............................................................................................................................................... 18
TABLE 7. PARALLEL LED PINS ..................................................................................................................................................... 18
TABLE 8. SERIAL MODE LED PINS ............................................................................................................................................... 20
TABLE 9. SPI FLASH INTERFACE PINS ......................................................................................................................................... 20
TABLE 10. UART INTERFACE PINS ............................................................................................................................................... 20
TABLE 11. CPU INTERFACE PINS .................................................................................................................................................. 21
TABLE 12. GPIO INTERFACE PINS ................................................................................................................................................ 21
TABLE 13. CONFIGURATION STRAPPING PINS ............................................................................................................................... 22
TABLE 14. CONFIGURATION STRAPPING PINS CONFIGURE NOTE .................................................................................................. 24
TABLE 15. MISCELLANEOUS PINS ................................................................................................................................................. 24
TABLE 16. TEST PINS .................................................................................................................................................................... 25
TABLE 17. POWER AND GND PINS ................................................................................................................................................ 26
TABLE 18. MEDIA DEPENDENT INTERFACE PIN MAPPING ............................................................................................................ 28
TABLE 19. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE ......................................................................................... 32
TABLE 20. LED DEFINITIONS........................................................................................................................................................ 39
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