verilog编写的计数器（4种）

module test(out,clk);
output[4:0] out;
input clk;
reg[4:0] out;
always @(posedge clk)
begin
out<=out+1; //计数
end
endmodule





module test(out,reset,clk,en);
output[3:0] out;
input reset,clk;
input en;
reg[3:0] out;
always @(posedge clk)
begin
if (reset) out<=0; //同步复位
else if(en==1)
out<=out+1; //计数
end
endmodule



module test(out,reset,clk,load,data);