ECS 精英電腦 主板線路圖 型號 p4m890t-m2_v10b-0627.pdf
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2010-02-22
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Title
Size Document Number Rev
Date: Sheet
of
1.0B
<OrgAddr1>
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1
32Thursday, June 01, 2006
Cover Page
P4M890T-M2
Elitegroup Computer Systems
Title
Size Document Number Rev
Date: Sheet
of
1.0B
<OrgAddr1>
Custom
1
32Thursday, June 01, 2006
Cover Page
P4M890T-M2
Elitegroup Computer Systems
Title
Size Document Number Rev
Date: Sheet
of
1.0B
<OrgAddr1>
Custom
1
32Thursday, June 01, 2006
Cover Page
P4M890T-M2
Elitegroup Computer Systems
P4M890T-M2
NB P4M890 (CPU)
Power (CPU Vcore)
Cover Page
SB VT8237R+/8237A(PCI, USB)
SB VT8237R+/8237A(V-Link, MII, ROM), TPM
NB P4M890 (PCI-E, V-Link)
Clock Generator, Clock Buffer
NB P4M890 (MEM)
USB, PS2, IDE
CPU P4-775(FSB)
AUDIO(ALC655/ALC883),CODEC
PCI 1, PCI 2
Block Diagram
DDR Terminator
CPU P4-775(PWR, GND)
COM*2, LPT, VGA
Power (DC to DC)
1
2
3
4
5
6
7
8
9
10
14
17
15
12
20
18
19
16
13
11
24
21
22
23
Front Panel, FAN, ATX24P
Super IO(ITE8712F/KX), FDD
LAN PHY(VT6103L)
PCI Express Slot X16, X1, CNR slot
SB VT8237R+/8237A(IDE, GPIO, AC-Link, SATA)
PCB
Gerber Out
244*244*1.6 -2116
Schematics
Schedule
Schematics
A
Layout M/B return
BOM
Rev : 1.0B
L2:PWR
L3:GND
25
VDIMM & DDR VTT
26
27
28
DDR II SLOT1
DDR II SLOT2
NB P4M890 (VGA)
Rev:A Initial version
1.Base on P4M890-M(B).
Customer:China SI
2/28~3/3
PCB:244*244mm
AUDIO(ALC655/ALC883),Connector
Lead-Free
29
CLOCK DIAGRAM
POWER SEQUENCE
RoHS
IC
GPIO(PIN)
Function
Note
VT
8237R+
GPI23(P21)
GPI8(AC9) -IDE1 cable detect
-IDE2 cable detect
GPO10(R25)
GPO11(T23)
V_DIMM volt adjust 0
V_DIMM volt adjust 1
GPI18(Y4)
GPI19(U23)
-PCIE PME SCI
-PCIE Hot Plug SCI
GPO7(R2) -TBL(Top Block Lock)
GPO5(AC7) -WP_ROM
default=0
default=1
IO
8712KX
GP10(84)
GP53(77)
MSG LED1
MSG LED2
GP41(78) CTRL USB/PS2 volt in S5 default=1
GP25(22)
GP26(21) CPU volt adjust 1
CPU volt adjust 0
GP23(24) CTRL over clock 1:enable
GPIO
8237R+,ALC655
A
SVID:1019(ECS)
SSID:2171(Q71)
Purple
GPO29 PCIE resetOD
O
OD
OD
O
GP20(27)
GP21(26) CFG2
CFG1 default=0
default=0
8237A,ALC883
DDR SLOTS
RTL8110SC/RTL8100C
30
31
32
1394(VT6308P/6307)
3/4~3/12 3/12(3/16) 3/22
4.DDR*2 + DDRII*2
5.LAN(PHY,8100C,8110SC)
6.TPM(JLPC header)
2.VR11
3.Support CPU:CONROE
15-Q74-010010
15-Q74-010010
Purple
20/10
30/10
1.0
1.0
8237R+,ALC655
8237A,ALC883
81-685-Q74000
81-685-Q74001
Rev:A to 1.0
3/27
1.Update CPU:CONROE circuit(BPM0,VTT_SEL).
3.1394 routing:-INT_C => -INT_D
4.ALC655 add 100uF*2 for line out.
5.PCLK_ROM share with PCLK_SIO
2.VTT_SEL control VTT_CPU power.
6.Upper V_DIMM voltage:1.82V/2.54V
7.NB add pin AB32(CPUSLPIN#) for P4M900
4/6
8.DCLK[0:5]+/- del 799mil(stub length).
15-Q74-011000
Purple
Purple
15-Q74-011000
150/60/12
89-386-Q74100
89-386-Q74101
81-685-Q74100
81-685-Q74101
1.0A
1.0A
4/11
Rev:1.0 to 1.0A
1.VCC3 transfer to +1.5V_NB
2.CPU voltage adjustment.
15-Q74-011010
Purple 4/13 150/60/12
3.add F_MIC2.
8237A,ALC883
8237R+,ALC655
89-386-Q74110
Rev:1.0A to 1.0B
1.Conroe clock latch issue.
2.Add BSEL2 and level shift.
3.Modify VTT_SEL circuit.
4.Add cap for USB PLL&VCC25 power.
1.0B 6/1
8237R+,ALC655
5.Super I/O:serial 22 ohm on 5VSB, Vbat add 1uF.
剩余31页未读，继续阅读
资源评论
haixing2412012-06-15很真实，对照着修好了1块主板，谢谢！
