Preface
ARM DDI 0100E
Copyright © 1996-2000 ARM Limited. All rights reserved.
v
Architecture versions and variants
The ARM instruction set architecture has evolved significantly since it was first developed, and will
continue to be developed in the future. In order to be precise about which instructions exist in any particular
ARM implementation, five major versions of the instruction set have been defined to date. These are
denoted by the version numbers 1 to 5.
Many of the versions can be qualified with variant letters to specify collections of additional instructions
that are included in that version. These collections vary from being very small (the M variant denotes the
addition of just four extra instructions) to very large (the T variant denotes the addition of the entire Thumb
instruction set).
The five versions of the ARM instruction set architecture to date are as follows:
Version 1 This version was implemented only by ARM1, and was never used in a commercial product.
It contained:
• the basic data-processing instructions (not including multiplies)
• byte, word, and multi-word load/store instructions
• branch instructions, including a branch-and-link instruction designed for subroutine
calls
• a software interrupt instruction, for use in making Operating System calls.
Version 1 only had a 26-bit address space, and is now obsolete.
Version 2 This version extended architecture version 1 by adding:
• multiply and multiply-accumulate instructions
• coprocessor support
• two more banked registers in fast interrupt mode
• atomic load-and-store instructions called SWP and SWPB (in a slightly later variant
called version 2a).
Versions 2 and 2a still only had a 26-bit address space, and are now obsolete.
Version 3 This architecture version extended the addressing range to 32 bits. Program status
information which had previously been stored in R15 was moved to a new Current Program
Status Register (CPSR), and Saved Program Status Registers (SPSRs) were added to
preserve the CPSR contents when an exception occurred. As a result, the following changes
occurred to the instruction set:
• two instructions (MRS and MSR) were added to allow the new CPSR and SPSRs to be
accessed.
• the functionality of instructions previously used to return from exceptions was
modified to allow them to continue to be used for that purpose.
Version 3 also added two new processor modes in order to make it possible to use Data
Abort, Prefetch Abort and Undefined Instruction exceptions effectively in Operating
System code.
Backwards-compatibility support for the 26-bit architectures was obligatory in version 3,
except in a variant called version 3G. The distinction between versions 3 and 3G is now
obsolete.
