ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture (PDF)

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ARM官方的ARM架构参考手册,最新版本ARMv8-A,是系统学习ARM指令的最好参考书。Architecture Reference Manual ARMv8 汇编指令手册。
This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word"partner"in reference to ARMs customers is not intended to create or refer to any partnership relationship with any other company. ARM may make changes to this document at any time and without notice If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement specifically covering this document with ARM, then the signed written agreement prevails over and supersedes the conflicting provisions of these lerins Words and logos marked with or are registered trademarks or trademarks of arm limited or its affiliates in the eu and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respectiv ownersYoumustfollowtheArmtrademarkusageguidelineshttp://www.arm.com/about/trademarks/guidelines/index.php Copyright C) 2013-2017 ARM Limited or its affiliates. All rights reserved ARM Limited Company 02557590 registered in England 110 Fulbourn Road, Cambridge, England CB1 9NJ LES-PRE-20327 In this documcnt, whcrc thc tcrm ARM is uscd to rcfcr to thc company it mcans"ARM or any of its subsidiaries as appropriate Note The term ARM can refer to versions of the ArM architecture, for example ArMv& refers to version 8 of the ARM architecture. The context makes it clear when the term is used in this way This document describes only the armv8-A architecture profile. For the behaviors required by the previous version of this architecture profile, ARMv7-A, see the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by arm and the party that arm delivered this document to Product Status Apart from the exceptions listed in Limitations of issue B a, the information in this document is final, that is for a developed product. The exceptions have a Beta quality status, which means that they are work-in-progre Web address http://www.arm.com Limitations of issue ba This issue B a of the ARMv8 Architecture Reference Manual contains many improvements and corrections. Validation of this document has identified the following issues that aRm will address in future issues The descriptions of the following architectural extensions are of beta quality and remain work in progress The ARMy8 2 architectural extension The Reliability, Availability, and Serviceability(ras)Extension The scalable vector Extension (SVE In descriptive text, bcta-quality information is colored red to show that it is work-in-progrcss. This quality status applics both to the colored text and to rclatcd contcnt in pscudocodc, in register dcscriptions, and in instruction descriptions that relate to these features The ARMv8 2 architectural extension also supports the following optional features that will be documented in a future issue of this manual The Dot Product feature that provides support for UDOT and SDOT instructions The Cryptographic feature that supports additional sha and Cryptographic algorithms In consultation with architectural partners arm has changed the formal definition of the arm memory model, and the ncw dcfinition forms part of this Manual. Whilc this redefinition has a significant impact on the structurc of the memory model chapters, and on the conceptual framework and terminology used to describe the memory architecture, it has no practical implications for implementations of the ARMv8-A architecture ARM DDI 0487B a Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. D033117 Non-Confidential Appendix K10 ARM Pseudocode Definition requires further review and update. Since this appendix is informative, rather than being part of the architecture specification, this does not affect the quality status of this release Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. ARM DD 0487B a Non-Confidential D033117 Contents ARM Architecture Reference Manual arMv8 for ARMV8-A architecture profile Preface About this manual XVI Using this manual XVIll Conventions 1aaaa“面11面 XXIII Additional reading Feedback Part a ARMV8 Architecture Introduction and overview Chapter a1 Introduction to the army architecture al.1 About the arm architecture A130 A1.2 Architecture profiles A1-32 A1.3 ARMv8 architectural concepts A1-34 A1. 4 Supported data types A1-38 A1.5 Floating-point and Advanced SIMD support A1-48 A1.6 The ARM memory model A154 Al.7 ARMy8 architecture extensions A1-55 Part B The AArch64 Application Level Architecture Chapter B The AArch64 Application Level Programmers' Model B1.1 About the Application level programmers model .B170 B1.2 Registers in Aarch 64 Execution state B1-71 B1.3 Software control features and elo B176 ARM DDI 0487B a Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. D033117 Non-Confidential Contents Chapter B2 The AArch64 Application Level Memory Model B2. 1 About the ARM memory model B280 B2.2 Atomicity in the ARM architecture B282 B2. 3 Definition of the ARMv8 memory model B2-86 B2. 4 Caches and memory hierarchy .B2-97 B2.5 Alignment support B2-102 B2.6 Endian support B2-104 B2.7 Memory types and attributes B2-107 B2.8 Mismatched memory attributes B2-118 B2. 9 Synchronization and semaphores B2-121 Part c The aarch64 Instruction set Chapter C1 The a64 Instruction set Cl1 About the a64 instruction set C1136 C1.2 Structure of the A64 assembler language C1-137 C1.3 Address generation C1-143 C1, 4 Instruction aliases ..C1-146 Chapter C2 About the A64 Instruction Descriptions C2. 1 Understanding the a64 instruction descriptions .C2-148 C2.2 General information about the a64 instruction descriptions C2-151 Chapter C3 A64 Instruction Set Overview C3.1 Branches, Exception generating, and System instructions C3-156 C3.2 Loads and stores C3-160 C3.3 Data processing-immediate C3-176 C3.4 Data processing-register C3-181 C3.5 Data processing-SIMD and floating-point C3-189 Chapter C4 A64 Instruction Set Encoding C4. 1 A64 instruction set encoding C4-210 Chapter C5 The A64 System Instruction Class C5. 1 The System instruction class encoding space C5-312 C52 Special-purpose registers C5-336 C5.3 A64 system instructions for cache maintenance C5-405 C5 4 A64 system instructions for address translation C5-427 C55 A64 system instructions for TLB maintenance c5-454 Chapter C6 A64 Base Instruction Descriptions c6. 1 About the a64 base instructions .:“ C6-518 C62 Alphabetical list of A64 base instructions C6520 Chapter c7 A64 Advanced SIMD and Floating-point Instruction Descriptions C7.1 About the A64 SIMD and floating-point instructions C7-976 C7.2 Alphabetical list of A64 floating-point and Advanced SIMD instructions C7978 Part d The AArch64 System Level Architecture Chapter D1 The AArch64 System Level Programmers' Model D1.1 Exception levels D11776 D1.2 EXception terminology ..... D1-1777 D1.3 Execution state 1-1779 D1. 4 Security state D1-1780 Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. ARM DD 0487B a Non-Confidential D033117 Contents D1.5 Virtualization D1-1782 D1.6 Registers for instruction processing and exception handling D1-1785 D1.7 Process state, PStATE D1-179 D1. 8 Program counter and stack pointer alignment D1-1793 D19 Reset 1-1795 D1.10 Exception entry D1-1799 D1.11 Exception return D1-1815 D1.12 The Exception level hierarchy D1-1819 D1.13 Synchronous exception types, routing and priorities ∴D1-1826 D1.14 Asynchronous exception types, routing, masking and priorities D1-1834 D1.15 Configurable instruction enables and disables and trap controls D1-1842 D1.16 System calls 1-1878 D1.17 Mechanisms for entering a low-power state D1-1879 D1.18 Self-hosted debug D11884 D1.9 The Performance monitors extension D11886 D1. 20 Interprocessing D1-1887 D1. 21 The effect of implementation choices on the programmers'model...... D1-1899 Chapter D2 AArch64 Self-hosted Debug D2.1 About self-hosted debug D2-1906 D2.2 The debug exception enable controls D2-1910 D2.3 Routing debug exceptions D2-1911 D2. 4 Enabling debug exceptions from the current Exception level and Security state D2-1913 D2.5 The effect of powerdown on debug exceptions D2-1915 D2.6 Summary of the routing and enabling of debug exceptions D2-1916 D2.7 Pseudocode description of debug exceptions 21918 D2.8 Breakpoint Instruction exceptions .D2-1919 D2. 9 Breakpoint exceptions D2-1921 D2. 10 Watchpoint exceptions D2-1940 D2. 11 Vector Catch exceptions D2-1955 D2. 12 Software Step exceptions D2-1956 D2.13 Synchronization and debug exceptions D21970 Chapter D3 The Aarch64 System Level Memory Model D3. 1 about the memory system architecture D3-1972 D3.2 Address space D3-1973 D3.3 Mixed-endian support .“ D3-1974 D3.4 Cache support D3-1975 D3.5 External aborts D3-1997 D3.6 Memory barrier instructions D3-1999 D3.7 Pseudocode description of general memory system instructions D3-2000 Chapter D4 The AArch64 Virtual Memory System Architecture D4. 1 About the Virtual Memory System Architecture(VMSA) D4-2004 D4.2 The VmsAv8-64 address translation system D4-2008 D4.3 VMSAv8-64 translation table format descriptors D4-2060 D4.4 Memory access control D4-2071 D4.5 Memory region attributes D4-2090 D4. 6 Virtualization host extensions D4-2098 D4.7 MMU faults D4-2103 D4.8 Translation Lookaside Buffers(TLBs)…… D4-2113 D4.9 TLB maintenance requirements and the tlb maintenance instructions.... D4-2119 D4.10 Caches in a MSAV8-64 implementation……..….,….,……….,b4-2133 Chapter d5 The Performance monitors extension D5.1 About the performance monitors D52138 D52 Accuracy of the Performance Monitors D5-2140 ARM DDI 0487B a Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. D033117 Non-Confidential Contents D5, 3 Behavior on overflow D5-2142 D5. 4 Attributability D5-2144 D5.5 Effect of el3 and el2 D5-2145 D5.6 Event filtering D5-2147 D57 Performance Monitors and debug state D5-2149 D5 8 Counter enables D5-2150 D5.9 Counter access D5-215 D5. 10 Events, event numbers and mnemonics.. D5-2152 D5. 11 Performance Monitors Extension registers ∴D5-2176 Chapter d6 The generic Timer in AArch 64 state D6.1 About the generic timer D6-2180 D6. 2 The aarch64 view of the generic timer ..D6-2184 Chapter d7 AArch64 System Register Descriptions D7.1 About the Aarch64 System registers D7-2190 D7.2 General system control registers D7-2198 D7. 3 Debug registers D7-2554 D7. 4 Performance Monitors registers D7-2629 D7.5 Generic Timer registers..................... D7-2672 Part E The AArch32 Application Level Architecture Chapter e1 The AArch32 Application Level Programmers'Model E11 About the Application level programmers'model E12728 E1.2 The Application level programmers' model in AArch32 state E1-2729 E1.3 Advanced SIMD and floating-point instructions E12740 E1. 4 About the aarch 32 System register interface .E1-2752 E1.5 Exceptions E12753 Chapter E2 The AArch32 Application Level Memory Model E2. 1 About the arm memory model E2-2756 E2.2 Atomicity in the ARM architecture E2-2758 E2.3 Definition of the ARMv8 memory model E2-2762 E2. 4 Caches and memory hierarchy E2-2772 E2.5 Alignment support E2-2777 E2.6 Endian support 2-2779 E2.7 Memory types and attributes E22782 E2.8 Mismatched memory attributes .E2-2792 E2.9 Synchronization and semaphores E2-2795 Part F The aarch 32 Instruction Sets Chapter F1 The Aarch32 Instruction sets Overview F1. 1 Support for instructions in different versions of the ARM architecture F1-2808 F12 Unified Assembler Language………… …F1-2809 F1.3 Branch instructions F1-2811 F1.4 Data-processing instructions ................. F12812 F1.5 PSTATE and banked register access instructions F1-2820 F1.6 Load /store instructions F1-2821 F1.7 Load/store multiple instructions F1-2824 F1.8 Miscellaneous instructions F1-2825 F1.9 EXception-generating and exception- handling instructions……… .F12827 F1.10 System register access instructions F1-2828 F1.11 Advanced siMD and floating- point load/store instructions .......... F1-2829 F1. 12 Advanced SIMD and floating-point register transfer instructions .F1-2831 Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. ARM DD 0487B a Non-Confidential D033117 Contents F1.13 Advanced sIMd data-processing instructions F1-2832 F1.14 Floating-point data-processing instructions F1-2840 Chapter F2 About the T32 and a32 Instruction Descriptions F2.1 Format of instruction descriptions .F22844 F2.2 Standard assembler syntax fields F2-2848 F2.3 Conditional execution .F2-2849 F2. 4 Shifts applied to a register.......... F2-2852 F2.5 Memory accesses F22854 F2.6 Encoding of lists of general-purpose registers and the Pc .F2-2855 F2.7 General information about the t32 and a32 instruction descriptions F2-2856 F2.8 Additional pseudocode support for instruction descriptions F2-2868 F2. 9 Additional information about Advanced sIMd and floating-point instructions. F2-2869 Chapter F3 T32 Instruction Set Encoding F3.1 T32 instruction set encoding F32876 F3.2 About the T32 Advanced SIMD and floating-point instructions and their encoding F3-2941 Chapter F4 A32 Instruction Set Encoding F4.1 A32 instruction set encoding F4-2944 F4.2 About the A32 Advanced SIMD and floating-point instructions and their encoding F4-3001 Chapter F5 T32 and A32 Base Instruction Set Instruction Descriptions F5. 1 Alphabetical list of t32 and A32 base instruction set instructions F5-3004 F52 Encoding and use of Banked register transter instructions F5-3674 Chapter F6 T32 and A32 Advanced sIMD and floating- point Instruction Descriptions F6. 1 Alphabetical list of floating-point and Advanced SIMD instructions F6-3680 Part G The AArch32 System Level Architecture Chapter G1 The AArch32 System Level Programmers'Model G1. 1 About the AArch32 System level programmers model G1-4308 G1.2 EXception levels…… ∴G14309 G1.3 EXception terminology G1-4310 G1.4 Execution state G1-4312 G1.5 Instruction Set state G1-4314 G1. 6 Security state G1-4315 G1. 7 Security state, Exception levels, and AArch 32 execution privilege G1-4318 G1 8 virtualization G1-4320 G1. 9 AArch32 PE modes, and general-purpose and Special-purpose registers.. G1-4322 G1. 10 Process state PStAtE G1-4332 G1.11 Instruction set states G14338 G1.12 Handling exceptions that are taken to an Exception level using AArch32 G14340 G1.13 Exception return to an exception level using aarch 32 G14360 G1.14 Asynchronous exception behavior for exceptions taken from AArch 32 state. G1-4365 G1.15 AArch32 state exception descriptions G1-4376 G1.16 Reset into Aarch 32 state G1-4399 G1. 17 Mechanisms for entering a low-power state G1-4403 G1. 18 The AArch32 System register interface G14408 G1.19 Advanced sIMd and floating-point support G14412 G1.20 Configurable instruction enables and disables, and trap controls G1-4418 Chapter G2 AArch32 Self-hosted Debug G2.1 About self-hosted debug G2-4454 ARM DDI 0487B a Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. D033117 Non-Confidential Contents G2.2 The debug exception enable controls G2-4458 G2.3 Routing debug exceptions G2-4459 G2. 4 Enabling debug exceptions from the current Privilege level and Security state G2-4461 G2.5 The effect of powerdown on debug exceptions G24463 G2.6 Summary of permitted routing and enabling of debug exceptions G2-4464 G2.7 Pseudocode description of debug exceptions G2-4466 G2. 8 Breakpoint Instruction exceptions G2-4467 G2. 9 Breakpoint exceptions .G2-4470 G2.10 Watchpoint exceptions G2-4496 G2. 11 Vector Catch exceptions G2-4510 G2. 12 Synchronization and debug exception G2-4518 Chapter G3 The AArch 32 System Level Memory Mod G3. 1 About the memory system architecture G3-4522 G3.2 Address space G3-4523 G3. 3 Mixed-endian support G34524 G3. 4 AArch32 cache and branch predictor support G3-4525 G3.5 System register support for IMPLEMENTATION DEFINED memory features G3-4549 G3.6 External aborts G3-4550 G3.7 Memory barrier instructions G3-4552 G3.8 Pseudocode description of general memory system instructions G3-4553 Chapter G4 The Aarch32 Virtual Memory System Architecture G4.1 About Vmsay8-32 G4-4558 G4.2 The effects of disabling address translation stages on VmsAv8-32 behavior G4-4567 G4.3 Translation tables G4-457 G4. 4 The VMSAv8-32 Short-descriptor translation table format G4-4576 G4.5 The VMSAv8-32 Long-descriptor translation table format G4-4585 G4.6 Memory access control G4-4605 G4.7 Memory region attributes G4-4616 G4.8 Translation Lookaside Buffers (TLBs) G4-4628 G4. 9 TLB maintenance requirements G4-4632 G4. 10 Caches in VmsAv8-32 G4-4646 G4.11 VMSAV8-32 memory aborts G4-4649 G4.12 Exception reporting in a VMsAv8-32 implementation G4-4663 G4. 13 Address translation instructions G4-4682 G4.14 About the System registers for VMSA8-32………… G4-4689 G4.15 VMSAv8-32 organization of registers in the (coproc==ob 10)encoding space G4-4704 G4.16 VMSAv8-32 organization of registers in the(coproc==0b1111)encoding space G4-4707 G4.17 Functional grouping of VMSAv8-32 System registers .G4-4726 G4.18 Pseudocode description of VMSAv8-32 memory system operations G4-4748 Chapter G5 The Generic Timer in AArch 32 state G5.1 About the generic Timer in aarch 32 state G5-4752 G5.2 The Aarch 32 view of the generic timer G5-4756 Chapter G6 AArch32 System Register Descriptions G6. 1 About the AArch32 System registers .G6-4764 G6.2 General system control registers G6. 3 Debug registers G6-5239 G6. 4 Performance monitors registers G6-533 G6.5 Generic Timer registers G6-5383 X Copyright o 2013-2017 ARM Limited or its affiliates. All rights reserved. ARM DD 0487B a Non-Confidential D033117

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海神800 不错,好资源。
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litao6169 hao hao hao
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yirenyang 了解下ARM的V8
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